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google/reef: Add mainboard SMI handler 

This patch adds a mainboard SMI handler file which has
functions to set proper Wake mask before going to sleep
so that system can wake up on lidopen, key press etc.
Also SCI mask is set on boot which will enable timely update
of battery UI on charger connect/disconnect.

BUG = chrome-os-partner:53992
TEST = Reef Platform wakes from S3 on lidopen, key press and also
       sysfs entry for AC is updated on charger connect/disconnect.

Change-Id: I8c087994b48223b253dcf1cbb3ed3c3a0f366e36
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15615
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shaunak Saha 2016-07-11 21:04:25 -07:00 committed by Aaron Durbin
parent 141ce41112
commit 9a6ebda9b4
2 changed files with 71 additions and 0 deletions
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1
src/mainboard/google/reef/Makefile.inc
View File

@ -10,3 +10,4 @@ ramstage-y += ec.c
ramstage-y += mainboard.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

70
src/mainboard/google/reef/smihandler.c Normal file
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@ -0,0 +1,70 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/ec.h>
#include <soc/pm.h>
#include "ec.h"
void mainboard_smi_sleep(u8 slp_typ)
{
if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
return;
switch (slp_typ) {
case 3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
enable_gpe(GPIO_TIER_1_SCI);
break;
case 5:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != 0)
;
}
int mainboard_smi_apmc(u8 apmc)
{
if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
return 0;
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
break;
case APM_CNT_ACPI_DISABLE:
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
break;
}
return 0;
}