From 9a791dffeae2097aa0a18f645ce07acfed41b9bc Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Mon, 3 Apr 2006 20:38:34 +0000 Subject: [PATCH] new cache_as_ram support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/arch/i386/include/arch/romcc_io.h | 18 + src/config/Options.lb | 12 +- src/cpu/amd/car/cache_as_ram.inc | 6 +- src/cpu/amd/car/clear_init_ram.c | 59 + src/cpu/amd/car/copy_and_run.c | 22 +- src/cpu/amd/car/disable_cache_as_ram.c | 30 +- src/cpu/amd/car/post_cache_as_ram.c | 91 +- src/cpu/amd/model_fxx/init_cpus.c | 25 +- src/cpu/x86/lapic/lapic_cpu_init.c | 9 +- src/devices/hypertransport.c | 14 - src/include/cpu/x86/mem.h | 16 +- src/mainboard/agami/aruma/cache_as_ram_auto.c | 3 +- src/mainboard/amd/serengeti_leopard/Config.lb | 2 - .../amd/serengeti_leopard/cache_as_ram_auto.c | 53 +- src/mainboard/arima/hdama/Config.lb | 1 - .../broadcom/blast/cache_as_ram_auto.c | 3 +- src/mainboard/tyan/s2850/Config.lb | 1 - src/mainboard/tyan/s2850/cache_as_ram_auto.c | 29 +- src/mainboard/tyan/s2875/Config.lb | 1 - src/mainboard/tyan/s2875/cache_as_ram_auto.c | 30 +- src/mainboard/tyan/s2880/Config.lb | 1 - src/mainboard/tyan/s2880/cache_as_ram_auto.c | 29 +- src/mainboard/tyan/s2881/Config.lb | 1 - src/mainboard/tyan/s2881/cache_as_ram_auto.c | 29 +- src/mainboard/tyan/s2882/Config.lb | 1 - src/mainboard/tyan/s2882/cache_as_ram_auto.c | 29 +- src/mainboard/tyan/s2885/Config.lb | 1 - src/mainboard/tyan/s2885/cache_as_ram_auto.c | 29 +- src/mainboard/tyan/s2891/Config.lb | 4 +- src/mainboard/tyan/s2891/Options.lb | 28 +- src/mainboard/tyan/s2891/cache_as_ram_auto.c | 22 +- src/mainboard/tyan/s2891/get_bus_conf.c | 3 +- src/mainboard/tyan/s2891/resourcemap.c | 4 +- src/mainboard/tyan/s2892/Config.lb | 3 +- src/mainboard/tyan/s2892/Options.lb | 28 +- src/mainboard/tyan/s2892/cache_as_ram_auto.c | 22 +- src/mainboard/tyan/s2892/get_bus_conf.c | 2 +- src/mainboard/tyan/s2895/Options.lb | 23 +- src/mainboard/tyan/s2895/cache_as_ram_auto.c | 22 +- src/mainboard/tyan/s4880/Config.lb | 1 - src/mainboard/tyan/s4880/cache_as_ram_auto.c | 29 +- src/mainboard/tyan/s4882/Config.lb | 1 - src/mainboard/tyan/s4882/cache_as_ram_auto.c | 28 +- src/northbridge/amd/amdk8/coherent_ht.c | 9 + src/northbridge/amd/amdk8/coherent_ht_car.c | 1826 +++++++++++++++++ src/northbridge/amd/amdk8/incoherent_ht.c | 30 - src/northbridge/amd/amdk8/raminit.c | 4 + src/northbridge/amd/amdk8/reset_test.c | 34 + src/southbridge/amd/amd8111/Config.lb | 1 + .../amd/amd8111/amd8111_early_ctrl.c | 53 +- src/southbridge/amd/amd8111/amd8111_lpc.c | 8 +- src/southbridge/amd/amd8111/amd8111_reset.c | 28 +- .../nvidia/ck804/ck804_early_setup.c | 20 + .../nvidia/ck804/ck804_early_setup_car.c | 20 + .../nvidia/ck804/ck804_enable_rom.c | 1 + src/southbridge/nvidia/ck804/ck804_smbus.h | 16 +- targets/tyan/s2892/Config.lb | 4 +- targets/tyan/s2895/Config.lb | 6 +- 58 files changed, 2271 insertions(+), 554 deletions(-) create mode 100644 src/cpu/amd/car/clear_init_ram.c create mode 100644 src/northbridge/amd/amdk8/coherent_ht_car.c diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h index c0c2250f98..adda3f8ef8 100644 --- a/src/arch/i386/include/arch/romcc_io.h +++ b/src/arch/i386/include/arch/romcc_io.h @@ -178,6 +178,24 @@ static device_t pci_locate_device(unsigned pci_id, device_t dev) return PCI_DEV_INVALID; } +static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +{ + device_t dev, last; + + dev = PCI_DEV(bus, 0, 0); + last = PCI_DEV(bus, 31, 7); + + for(; dev <=last; dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; +} + + /* Generic functions for pnp devices */ static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value) diff --git a/src/config/Options.lb b/src/config/Options.lb index b5569673d7..1342366fe9 100644 --- a/src/config/Options.lb +++ b/src/config/Options.lb @@ -280,11 +280,17 @@ define DCACHE_RAM_BASE comment "Base address of data cache when using it for temporary RAM" end define DCACHE_RAM_SIZE - default none + default 0x1000 format "0x%x" - export used + export always comment "Size of data cache when using it for temporary RAM" end +define DCACHE_RAM_GLOBAL_VAR_SIZE + default 0 + format "0x%x" + export always + comment "Size of region that for global variable of cache as ram stage" +end define XIP_ROM_BASE default 0 format "0x%x" @@ -310,7 +316,7 @@ define CONFIG_UNCOMPRESSED end define CONFIG_LB_MEM_TOPK format "%d" - default 1024 + default 2048 export always comment "Kilobytes of memory to initialized before executing code from RAM" end diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index c7de4148a4..1cf141230b 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -1,8 +1,10 @@ /* by yhlu 6.2005 */ /* yhlu 2005.12 make it support HDT Memory Debuggers with Disassmbly, please select the PCI Bus mem for Phys Type*/ -/* We may need 4K bytes only */ +/* yhlu 2006.3 copy data from cache to ram and reserve 0x1000 for global variables */ #define CacheSize DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) +/* leave some space for global variable to pass to RAM stage */ +#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE #include #include @@ -147,7 +149,7 @@ clear_fixed_var_mtrr_out: #endif /*USE_FALLBACK_IMAGE == 1*/ /* set up the stack pointer */ - movl $(CacheBase+CacheSize-4), %eax + movl $(CacheBase+CacheSize - 4 - GlobalVarSize), %eax movl %eax, %esp /* Restore the BIST result */ diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c new file mode 100644 index 0000000000..593c0ddfd6 --- /dev/null +++ b/src/cpu/amd/car/clear_init_ram.c @@ -0,0 +1,59 @@ +/* by yhlu 6.2005 */ +/* be warned, this file will be used core 0/node 0 only */ + +static void __attribute__((noinline)) clear_init_ram(void) +{ + // gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram + // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already + // so noline clear_init_ram + clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); + +} + +/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/ +static inline __attribute__((always_inline)) void set_init_ram_access(void) +{ + __asm__ volatile ( + + "pushl %%ecx\n\t" + "pushl %%edx\n\t" + "pushl %%eax\n\t" + + /* enable caching for first 1M using variable mtrr */ + "movl $0x200, %%ecx\n\t" + "xorl %%edx, %%edx\n\t" + "movl $(0 | 6), %%eax\n\t" +// "movl $(0 | MTRR_TYPE_WRBACK), %%eax\n\t" + "wrmsr\n\t" + + "movl $0x201, %%ecx\n\t" + "movl $0x0000000f, %%edx\n\t" +#if CONFIG_USE_INIT + "movl %%esi, %%eax\n\t" +#else + "movl $((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), %%eax\n\t" +#endif + "wrmsr\n\t" + +#if 0 + /* enable caching for 64K using fixed mtrr */ + "movl $0x26e, %%ecx\n\t" /* fix4k_f0000*/ + "movl $0x1e1e1e1e, %%eax\n\t" /* WB MEM type */ + "movl %%eax, %%edx\n\t" + "wrmsr\n\t" + "movl $0x26f, %%ecx\n\t" /* fix4k_f8000*/ + "wrmsr\n\t" +#endif + + "popl %%eax\n\t" + "popl %%edx\n\t" + "popl %%ecx\n\t" + + : + : +#if CONFIG_USE_INIT + "S"((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800) +#endif + ); +} + diff --git a/src/cpu/amd/car/copy_and_run.c b/src/cpu/amd/car/copy_and_run.c index 55068c5511..68e9e35482 100644 --- a/src/cpu/amd/car/copy_and_run.c +++ b/src/cpu/amd/car/copy_and_run.c @@ -37,7 +37,7 @@ static inline void print_debug_cp_run(const char *strval, uint32_t val) #endif } -static void copy_and_run(unsigned cpu_reset) +static void copy_and_run(void) { uint8_t *src, *dst; unsigned long ilen = 0, olen = 0, last_m_off = 1; @@ -54,7 +54,7 @@ static void copy_and_run(unsigned cpu_reset) "subl %1, %2\n\t" : "=a" (src), "=b" (dst), "=c" (olen) ); - memcpy(src, dst, olen); + memcpy(dst, src, olen); #else __asm__ volatile ( @@ -65,14 +65,13 @@ static void copy_and_run(unsigned cpu_reset) print_debug_cp_run("src=",(uint32_t)src); print_debug_cp_run("dst=",(uint32_t)dst); - -// dump_mem(src, src+0x100); for(;;) { unsigned int m_off, m_len; while(GETBIT(bb, src, ilen)) { dst[olen++] = src[ilen++]; } + m_off = 1; do { m_off = m_off*2 + GETBIT(bb, src, ilen); @@ -109,24 +108,13 @@ static void copy_and_run(unsigned cpu_reset) } } #endif -// dump_mem(dst, dst+0x100); print_debug_cp_run("linxbios_ram.bin length = ", olen); print_debug("Jumping to LinuxBIOS.\r\n"); - if(cpu_reset == 1 ) { - __asm__ volatile ( - "movl $0xffffffff, %ebp\n\t" - ); - } - else { - __asm__ volatile ( - "xorl %ebp, %ebp\n\t" - ); - } - - __asm__ volatile ( + __asm__ volatile ( + "xorl %ebp, %ebp\n\t" /* cpu_reset for hardwaremain dummy */ "cli\n\t" "leal _iseg, %edi\n\t" "jmp *%edi\n\t" diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 06a558f413..56e60eefb7 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -3,10 +3,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) { __asm__ volatile ( - /* - FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that. - It is only needed if we want to go back - */ + /* We don't need cache as ram for now on */ /* disable cache */ "movl %cr0, %eax\n\t" @@ -43,5 +40,30 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) "movl %cr0, %eax\n\t" "andl $0x9fffffff,%eax\n\t" "movl %eax, %cr0\n\t" + ); } +/* be warned, this file will be used core 0 / node 0 and ram stack is ready*/ + +static void disable_cache_as_ram_bsp(void) +{ + __asm__ volatile ( + + "pushl %ecx\n\t" + "pushl %edx\n\t" + "pushl %eax\n\t" + + ); + + disable_cache_as_ram(); + + __asm__ volatile ( + + "popl %eax\n\t" + "popl %edx\n\t" + "popl %ecx\n\t" + + ); +} + + diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 345e4c34b0..0a91326b85 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -1,7 +1,9 @@ - +/* 2005.6 by yhlu + * 2006.3 yhlu add copy data from CAR to ram + */ #include "cpu/amd/car/disable_cache_as_ram.c" -#include "cpu/amd/car/clear_1m_ram.c" +#include "cpu/amd/car/clear_init_ram.c" static inline void print_debug_pcar(const char *strval, uint32_t val) { @@ -12,11 +14,18 @@ static inline void print_debug_pcar(const char *strval, uint32_t val) #endif } - - -static void post_cache_as_ram(unsigned cpu_reset) +static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes) { + __asm__ volatile( + "cld\n\t" + "rep movsl\n\t" + : /* No outputs */ + : "S" (src), "D" (dest), "c" ((bytes)>>2) + ); +} +static void post_cache_as_ram(void) +{ #if 1 { @@ -30,60 +39,50 @@ static void post_cache_as_ram(unsigned cpu_reset) } #endif - print_debug_pcar("cpu_reset = ",cpu_reset); + unsigned testx = 0x5a5a5a5a; + print_debug_pcar("testx = ", testx); - if(cpu_reset == 0) { - print_debug("Clearing initial memory region: "); - } - print_debug("No cache as ram now - "); + /* copy data from cache as ram to + ram need to set CONFIG_LB_MEM_TOPK to 2048 and use var mtrr instead. + */ +#if CONFIG_LB_MEM_TOPK <= 1024 + #error "You need to set CONFIG_LB_MEM_TOPK greater than 1024" +#endif + + set_init_ram_access(); - /* store cpu_reset to ebx */ + print_debug("Copying data from cache to ram -- switching to use ram as stack... "); + + /* from here don't store more data in CAR */ __asm__ volatile ( - "movl %0, %%ebx\n\t" - ::"a" (cpu_reset) + "pushl %eax\n\t" ); - - disable_cache_as_ram(); - - if(cpu_reset==0) { // cpu_reset don't need to clear it - clear_1m_ram(); - } - else { - set_1m_ram(); - } - + memcopy((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE, DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline __asm__ volatile ( /* set new esp */ /* before _RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t" - ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) ) + ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp + __asm__ volatile ( + "popl %eax\n\t" ); + /* We can put data to stack again */ - { - unsigned new_cpu_reset; + /* only global variable sysinfo in cache need to be offset */ + print_debug("Done\r\n"); + print_debug_pcar("testx = ", testx); - /* get back cpu_reset from ebx */ - __asm__ volatile ( - "movl %%ebx, %0\n\t" - :"=a" (new_cpu_reset) - ); + print_debug("Disabling cache as ram now \r\n"); + disable_cache_as_ram_bsp(); - print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/ + print_debug("Clearing initial memory region: "); + clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)), that is used as stack in ram + print_debug("Done\r\n"); - if(new_cpu_reset==0) { - print_debug("done\r\n"); - } else - { - print_debug("\r\n"); - } - - print_debug_pcar("new_cpu_reset = ", new_cpu_reset); - - - /*copy and execute linuxbios_ram */ - copy_and_run(new_cpu_reset); - /* We will not return */ - } + /*copy and execute linuxbios_ram */ + copy_and_run(); + /* We will not return */ print_debug("should not be here -\r\n"); diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 6a070d56ec..e60aa35bf9 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -1,7 +1,6 @@ //it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID #ifndef K8_SET_FIDVID #define K8_SET_FIDVID 0 - #endif #ifndef K8_SET_FIDVID_CORE0_ONLY @@ -42,7 +41,7 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core0_only, process_ap_t p j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3); if(nb_cfg_54) { if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation - e0_later_single_core = is_e0_later_in_bsp(i); // single core + e0_later_single_core = is_e0_later_in_bsp(i); // single core } if(e0_later_single_core) { j=1; @@ -204,7 +203,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) /* get the apicid, it may be lifted already */ apicid = lapicid(); -#if 1 +#if 0 // show our apicid, nodeid, and coreid if( id.coreid==0 ) { if (id.nodeid!=0) //all core0 except bsp @@ -219,21 +218,9 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) #endif if (cpu_init_detectedx) { - #if RAMINIT_SYSINFO == 1 - //We need to init sblnk and sbbusn, because it is called before ht_setup_chains_x - sysinfo->sblnk = get_sblnk(); - sysinfo->sbbusn = node_link_to_bus(0, sysinfo->sblnk); - #endif - print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detect from "); - - print_debug("\r\nIssuing SOFT_RESET...\r\n"); - - #if RAMINIT_SYSINFO == 1 - soft_reset(sysinfo); - #else - soft_reset(); - #endif - + print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detected from "); + print_debug("\r\nIssuing SOFT_RESET...\r\n"); + soft_reset(); } if(id.coreid==0) { @@ -256,8 +243,8 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) wait_cpu_state(bsp_apicid, 0x44); lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu + set_init_ram_access(); //inline disable_cache_as_ram(); // inline - set_1m_ram(); // inline stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... } diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index d7f7124deb..279101b74b 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -25,7 +25,7 @@ */ static unsigned long get_valid_start_eip(unsigned long orig_start_eip) { - return (unsigned long)orig_start_eip & 0xfffff; // 20 bit + return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 } static void copy_secondary_start_to_1m_below(void) @@ -43,7 +43,7 @@ static void copy_secondary_start_to_1m_below(void) code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; /* copy the _secondary_start to the ram below 1M*/ - memcpy(start_eip, (unsigned long)_secondary_start, code_size); + memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size); printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); #endif @@ -117,7 +117,12 @@ static int lapic_start_cpu(unsigned long apicid) return 0; } +#if _RAMBASE >= 0x100000 start_eip = get_valid_start_eip((unsigned long)_secondary_start); +#else + start_eip = (unsigned long)_secondary_start; +#endif + printk_debug("start_eip=0x%08lx\n", start_eip); num_starts = 2; diff --git a/src/devices/hypertransport.c b/src/devices/hypertransport.c index 10d4420fee..c61efa6c7b 100644 --- a/src/devices/hypertransport.c +++ b/src/devices/hypertransport.c @@ -424,17 +424,8 @@ unsigned int hypertransport_scan_chain(struct bus *bus, } flags &= ~0x1f; /* mask out base Unit ID */ -#if CK804_DEVN_BASE==0 - if((dev->vendor == 0x10de) && (dev->device == 0x005e)) { - next_unitid = 0; - } - else { -#endif flags |= next_unitid & 0x1f; pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags); -#if CK804_DEVN_BASE==0 - } -#endif /* Update the Unitd id in the device structure */ static_count = 1; @@ -473,11 +464,6 @@ unsigned int hypertransport_scan_chain(struct bus *bus, dev->vendor, dev->device, (dev->enabled? "enabled": "disabled"), next_unitid); -#if CK804_DEVN_BASE==0 - if ((dev->vendor == 0x10de) && (dev->device == 0x005e)) { - break; // CK804 can not change unitid, so it only can be alone in the link - } -#endif } while((last_unitid != next_unitid) && (next_unitid <= (max_devfn >> 3))); end_of_chain: diff --git a/src/include/cpu/x86/mem.h b/src/include/cpu/x86/mem.h index 4849ed289a..532fc79e0a 100644 --- a/src/include/cpu/x86/mem.h +++ b/src/include/cpu/x86/mem.h @@ -4,15 +4,13 @@ /* Optimized generic x86 assembly for clearing memory */ static inline void clear_memory(void *addr, unsigned long size) { - asm volatile( - "1: \n\t" - "movl %0, (%1)\n\t" - "addl $4, %1\n\t" - "subl $4, %2\n\t" - "jnz 1b\n\t" - : /* No outputs */ - : "a" (0), "D" (addr), "c" (size) - ); + asm volatile( + "cld \n\t" + "rep stosl\n\t" + : /* No outputs */ + : "a" (0), "D" (addr), "c" (size>>2) + ); + } #endif /* CPU_X86_MEM_H */ diff --git a/src/mainboard/agami/aruma/cache_as_ram_auto.c b/src/mainboard/agami/aruma/cache_as_ram_auto.c index b820c52aef..8d9e13cb45 100644 --- a/src/mainboard/agami/aruma/cache_as_ram_auto.c +++ b/src/mainboard/agami/aruma/cache_as_ram_auto.c @@ -204,7 +204,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; unsigned nodes; @@ -253,6 +252,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/amd/serengeti_leopard/Config.lb b/src/mainboard/amd/serengeti_leopard/Config.lb index b6ee7180ec..ea92f8e201 100644 --- a/src/mainboard/amd/serengeti_leopard/Config.lb +++ b/src/mainboard/amd/serengeti_leopard/Config.lb @@ -117,8 +117,6 @@ if HAVE_ACPI_TABLES end end -object reset.o - if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c index b81caf0406..965e439f49 100644 --- a/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c +++ b/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c @@ -10,21 +10,13 @@ //use by raminit #define K8_4RANK_DIMM_SUPPORT 1 -//use bu init_cpus -#if 0 - #define ENABLE_APIC_EXT_ID 1 - #define APIC_ID_OFFSET 0x10 - #define LIFT_BSP_APIC_ID 0 -#else - #define ENABLE_APIC_EXT_ID 0 -#endif - //used by incoherent_ht //#define K8_SCAN_PCI_BUS 1 //#define K8_ALLOCATE_IO_RANGE 1 #include #include +#include #include #include #include @@ -33,7 +25,6 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" -#include "ram/ramtest.c" #if 0 static void post_code(uint8_t value) { @@ -47,7 +38,6 @@ static void post_code(uint8_t value) { #endif #include -#include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -66,43 +56,11 @@ static void post_code(uint8_t value) { #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - unsigned sblnk = get_sblnk(); - - /* Find the device */ -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - dev = PCI_DEV(node_link_to_bus(0, sblnk), 2 + HT_CHAIN_END_UNITID_BASE - 1, 3); -#else - dev = PCI_DEV(node_link_to_bus(0, sblnk), 4 + HT_CHAIN_UNITID_BASE - 1, 3); -#endif - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} -static void soft_reset(void) -{ - device_t dev; - unsigned sblnk = get_sblnk(); - - /* Find the device */ -#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - dev = PCI_DEV(node_link_to_bus(0, sblnk), 2 + HT_CHAIN_END_UNITID_BASE - 1, 0); -#else - dev = PCI_DEV(node_link_to_bus(0, sblnk), 4 + HT_CHAIN_UNITID_BASE - 1, 0); -#endif - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -254,7 +212,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -296,7 +253,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) if (needs_reset) { print_info("ht reset -\r\n"); - soft_reset(); + soft_reset(); } allow_all_aps_stop(bsp_apicid); @@ -327,6 +284,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_devices(); #endif - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb index 8b38b0a95b..3f709dff8c 100644 --- a/src/mainboard/arima/hdama/Config.lb +++ b/src/mainboard/arima/hdama/Config.lb @@ -45,7 +45,6 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o ## ## Romcc output diff --git a/src/mainboard/broadcom/blast/cache_as_ram_auto.c b/src/mainboard/broadcom/blast/cache_as_ram_auto.c index 37c1fd79dc..3ed4001a9f 100644 --- a/src/mainboard/broadcom/blast/cache_as_ram_auto.c +++ b/src/mainboard/broadcom/blast/cache_as_ram_auto.c @@ -190,7 +190,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -269,6 +268,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_pci_devices(); #endif - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb index 1916fa70c3..e227bc1542 100644 --- a/src/mainboard/tyan/s2850/Config.lb +++ b/src/mainboard/tyan/s2850/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM diff --git a/src/mainboard/tyan/s2850/cache_as_ram_auto.c b/src/mainboard/tyan/s2850/cache_as_ram_auto.c index ba01699c07..5ca8561ea7 100644 --- a/src/mainboard/tyan/s2850/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2850/cache_as_ram_auto.c @@ -47,31 +47,7 @@ static void post_code(uint8_t value) { #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -200,7 +176,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -235,5 +210,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb index b1052752fb..13596a2bec 100644 --- a/src/mainboard/tyan/s2875/Config.lb +++ b/src/mainboard/tyan/s2875/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM diff --git a/src/mainboard/tyan/s2875/cache_as_ram_auto.c b/src/mainboard/tyan/s2875/cache_as_ram_auto.c index 43ccb2702e..4126f49448 100644 --- a/src/mainboard/tyan/s2875/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2875/cache_as_ram_auto.c @@ -36,32 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -198,7 +173,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -231,6 +205,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index 9d7e015b32..d6f907f387 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM diff --git a/src/mainboard/tyan/s2880/cache_as_ram_auto.c b/src/mainboard/tyan/s2880/cache_as_ram_auto.c index 3808e83bbf..ab73876184 100644 --- a/src/mainboard/tyan/s2880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2880/cache_as_ram_auto.c @@ -37,31 +37,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -197,7 +173,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -232,5 +207,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb index 3b0cd33dd7..598f9b4a36 100644 --- a/src/mainboard/tyan/s2881/Config.lb +++ b/src/mainboard/tyan/s2881/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s2881/cache_as_ram_auto.c b/src/mainboard/tyan/s2881/cache_as_ram_auto.c index 77dd978856..67a32140ad 100644 --- a/src/mainboard/tyan/s2881/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2881/cache_as_ram_auto.c @@ -42,31 +42,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -185,7 +161,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -234,5 +209,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb index 8b173bd6d6..42c193be58 100644 --- a/src/mainboard/tyan/s2882/Config.lb +++ b/src/mainboard/tyan/s2882/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM diff --git a/src/mainboard/tyan/s2882/cache_as_ram_auto.c b/src/mainboard/tyan/s2882/cache_as_ram_auto.c index 967f068d51..c31181a8e2 100644 --- a/src/mainboard/tyan/s2882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2882/cache_as_ram_auto.c @@ -36,31 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -200,7 +176,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -235,6 +210,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb index 37b0d90522..2a035a35ab 100644 --- a/src/mainboard/tyan/s2885/Config.lb +++ b/src/mainboard/tyan/s2885/Config.lb @@ -44,7 +44,6 @@ driver mainboard.o object get_bus_conf.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM diff --git a/src/mainboard/tyan/s2885/cache_as_ram_auto.c b/src/mainboard/tyan/s2885/cache_as_ram_auto.c index 7b2ccfaa14..0c5792565c 100644 --- a/src/mainboard/tyan/s2885/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2885/cache_as_ram_auto.c @@ -36,31 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -185,7 +161,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -234,6 +209,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb index 9c460066c9..67c7b3c8a9 100644 --- a/src/mainboard/tyan/s2891/Config.lb +++ b/src/mainboard/tyan/s2891/Config.lb @@ -237,7 +237,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 off # Keyboard + device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 @@ -314,7 +314,7 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 7.0 on end - # register "rom_address" = "0xfff80000" #for 512K + # register "rom_address" = "0xfff80000" #for 512K register "rom_address" = "0xfff00000" #for 1M end end diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb index e87a4df341..9018364663 100644 --- a/src/mainboard/tyan/s2891/Options.lb +++ b/src/mainboard/tyan/s2891/Options.lb @@ -54,6 +54,7 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses K8_HW_MEM_HOLE_SIZEK +uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM uses DCACHE_RAM_BASE @@ -66,6 +67,13 @@ uses LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_LB_MEM_TOPK + ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes #default ROM_SIZE=524288 @@ -131,6 +139,22 @@ default CONFIG_LOGICAL_CPUS=1 #1G memory hole default K8_HW_MEM_HOLE_SIZEK=0x100000 +#Opteron K8 1G HT Support +default K8_HT_FREQ_1G_SUPPORT=1 + +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0x0 + +##real SB Unit ID, default is 0x20, mean dont touch it at last +#default HT_CHAIN_END_UNITID_BASE=0x0 + +#make the SB HT chain on bus 0, default is not (0) +default K8_SB_HT_CHAIN_ON_BUS0=2 + +##only offset for SB chain?, default is yes(1) +default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + + #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -144,9 +168,9 @@ default CONFIG_PCI_ROM_RUN=1 default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 -default ENABLE_APIC_EXT_ID=1 +default ENABLE_APIC_EXT_ID=0 default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=0 diff --git a/src/mainboard/tyan/s2891/cache_as_ram_auto.c b/src/mainboard/tyan/s2891/cache_as_ram_auto.c index 61edc58cd2..1bc29d9304 100644 --- a/src/mainboard/tyan/s2891/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2891/cache_as_ram_auto.c @@ -42,25 +42,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - set_bios_reset(); -#if 1 - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif -} - static void memreset_setup(void) { } @@ -197,7 +178,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -246,5 +226,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c index 92fefa6a0c..3462a5f557 100644 --- a/src/mainboard/tyan/s2891/get_bus_conf.c +++ b/src/mainboard/tyan/s2891/get_bus_conf.c @@ -152,9 +152,10 @@ void get_bus_conf(void) else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); - bus_8131_0 = bus_ck804_5+1; } + bus_8131_0 = (pci1234[1] >> 16) & 0xff; + /* 8131-1 */ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); if (dev) { diff --git a/src/mainboard/tyan/s2891/resourcemap.c b/src/mainboard/tyan/s2891/resourcemap.c index c55d95bb99..625e19f11c 100644 --- a/src/mainboard/tyan/s2891/resourcemap.c +++ b/src/mainboard/tyan/s2891/resourcemap.c @@ -186,7 +186,7 @@ static void setup_s2891_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, +// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -216,7 +216,7 @@ static void setup_s2891_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, +// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb index dcb0c45abf..6fa8e5d44a 100644 --- a/src/mainboard/tyan/s2892/Config.lb +++ b/src/mainboard/tyan/s2892/Config.lb @@ -313,7 +313,8 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" + # register "rom_address" = "0xfff80000" #for 512K + register "rom_address" = "0xfff00000" #for 1M end chip drivers/pci/onboard device pci 8.0 on end diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb index a8bac76536..7000126a5d 100644 --- a/src/mainboard/tyan/s2892/Options.lb +++ b/src/mainboard/tyan/s2892/Options.lb @@ -54,18 +54,24 @@ uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses K8_HW_MEM_HOLE_SIZEK +uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM uses DCACHE_RAM_BASE uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY + ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -default ROM_SIZE=524288 +#default ROM_SIZE=524288 #1M bytes -#default ROM_SIZE=1048576 +default ROM_SIZE=1048576 ## @@ -125,6 +131,21 @@ default CONFIG_LOGICAL_CPUS=1 #1G memory hole default K8_HW_MEM_HOLE_SIZEK=0x100000 +#Opteron K8 1G HT Support +default K8_HT_FREQ_1G_SUPPORT=1 + +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0x0 + +##real SB Unit ID, default is 0x20, mean dont touch it at last +#default HT_CHAIN_END_UNITID_BASE=0x0 + +#make the SB HT chain on bus 0, default is not (0) +default K8_SB_HT_CHAIN_ON_BUS0=2 + +##only offset for SB chain?, default is yes(1) +default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -138,8 +159,7 @@ default CONFIG_PCI_ROM_RUN=1 default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 - +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC diff --git a/src/mainboard/tyan/s2892/cache_as_ram_auto.c b/src/mainboard/tyan/s2892/cache_as_ram_auto.c index 3bb7fb3d83..1936563518 100644 --- a/src/mainboard/tyan/s2892/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2892/cache_as_ram_auto.c @@ -36,25 +36,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - set_bios_reset(); -#if 1 - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif -} - static void memreset_setup(void) { } @@ -210,7 +191,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -246,5 +226,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c index 92fefa6a0c..6086aa5ff5 100644 --- a/src/mainboard/tyan/s2892/get_bus_conf.c +++ b/src/mainboard/tyan/s2892/get_bus_conf.c @@ -152,9 +152,9 @@ void get_bus_conf(void) else { printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e); - bus_8131_0 = bus_ck804_5+1; } + bus_8131_0 = (pci1234[1] >> 16) & 0xff; /* 8131-1 */ dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); if (dev) { diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index 49b0e0b0de..c3f8ba3f8c 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -64,12 +64,17 @@ uses ENABLE_APIC_EXT_ID uses APIC_ID_OFFSET uses LIFT_BSP_APIC_ID +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY + ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -default ROM_SIZE=524288 +#default ROM_SIZE=524288 #1M bytes -#default ROM_SIZE=1048576 +default ROM_SIZE=1048576 ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use @@ -134,6 +139,18 @@ default K8_HW_MEM_HOLE_SIZEK=0x100000 #Opteron K8 1G HT Support default K8_HT_FREQ_1G_SUPPORT=1 +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0x0 + +##real SB Unit ID, default is 0x20, mean dont touch it at last +#default HT_CHAIN_END_UNITID_BASE=0x0 + +#make the SB HT chain on bus 0, default is not (0) +default K8_SB_HT_CHAIN_ON_BUS0=2 + +##only offset for SB chain?, default is yes(1) +default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + #VGA default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 @@ -144,7 +161,7 @@ default CONFIG_PCI_ROM_RUN=1 default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 default ENABLE_APIC_EXT_ID=1 default APIC_ID_OFFSET=0x10 diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c index 1ae0c9e5d1..00bf1a6c23 100644 --- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c @@ -50,25 +50,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1) -static void hard_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - set_bios_reset(); -#if 1 - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif -} - static void memreset_setup(void) { } @@ -239,7 +220,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -288,5 +268,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb index 74c5542f87..54fc432d72 100644 --- a/src/mainboard/tyan/s4880/Config.lb +++ b/src/mainboard/tyan/s4880/Config.lb @@ -43,7 +43,6 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s4880/cache_as_ram_auto.c b/src/mainboard/tyan/s4880/cache_as_ram_auto.c index 0165a1f8c2..1a16eff09f 100644 --- a/src/mainboard/tyan/s4880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4880/cache_as_ram_auto.c @@ -36,31 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -247,7 +223,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; if (bist == 0) { init_cpus(cpu_init_detectedx); @@ -281,5 +256,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index 1913120393..05e898814e 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -43,7 +43,6 @@ arch i386 end driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -object reset.o if USE_DCACHE_RAM if CONFIG_USE_INIT diff --git a/src/mainboard/tyan/s4882/cache_as_ram_auto.c b/src/mainboard/tyan/s4882/cache_as_ram_auto.c index 6f1ac8d098..2b463d4d27 100644 --- a/src/mainboard/tyan/s4882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4882/cache_as_ram_auto.c @@ -36,31 +36,8 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - device_t dev; - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3); - - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - device_t dev; - - /* Find the device */ - dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0); - - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); -} +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -222,7 +199,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned cpu_reset = 0; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; @@ -271,6 +247,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); sdram_initialize(nodes, ctrl); - post_cache_as_ram(cpu_reset); + post_cache_as_ram(); } diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 7d43f3c97d..d29831b74b 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -1,3 +1,10 @@ +#if USE_DCACHE_RAM + +#include "coherent_ht_car.c" + +#else + + /* coherent hypertransport initialization for AMD64 * * written by Stefan Reinauer @@ -1824,3 +1831,5 @@ static int setup_coherent_ht_domain(void) result.needs_reset = optimize_link_read_pointers(result.nodes, result.needs_reset); return result.needs_reset; } + +#endif diff --git a/src/northbridge/amd/amdk8/coherent_ht_car.c b/src/northbridge/amd/amdk8/coherent_ht_car.c new file mode 100644 index 0000000000..5b9a87ac63 --- /dev/null +++ b/src/northbridge/amd/amdk8/coherent_ht_car.c @@ -0,0 +1,1826 @@ +/* coherent hypertransport initialization for AMD64 + * + * written by Stefan Reinauer + * (c) 2003-2004 by SuSE Linux AG + * + * (c) 2004 Tyan Computer + * 2004.12 yhlu added support to create routing table dynamically. + * it also support 8 ways too. (8 ways ladder or 8 ways crossbar) + * + * This code is licensed under GPL. + */ + +/* + * This algorithm assumes a grid configuration as follows: + * + * nodes : 1 2 4 6 8 + * org. : 1x1 2x1 2x2 2x3 2x4 + Ladder: + CPU7-------------CPU6 + | | + | | + | | + | | + | | + | | + CPU5-------------CPU4 + | | + | | + | | + | | + | | + | | + CPU3-------------CPU2 + | | + | | + | | + | | + | | + | | + CPU1-------------CPU0 + CROSS_BAR_47_56: + CPU7-------------CPU6 + | \____ ___/ | + | \ / | + | \/ | + | /\ | + | / \ | + | ____/ \___ | + CPU5 CPU4 + | | + | | + | | + | | + | | + | | + CPU3-------------CPU2 + | | + | | + | | + | | + | | + | | + CPU1-------------CPU0 + */ + +#include +#include +#include +#include "arch/romcc_io.h" + +#include "amdk8.h" + +#define enable_bsp_routing() enable_routing(0) + +#define NODE_HT(x) PCI_DEV(0,24+x,0) +#define NODE_MP(x) PCI_DEV(0,24+x,1) +#define NODE_MC(x) PCI_DEV(0,24+x,3) + +#define DEFAULT 0x00010101 /* default row entry */ + +typedef uint8_t u8; +typedef uint32_t u32; + +#ifndef CROSS_BAR_47_56 + #define CROSS_BAR_47_56 0 +#endif + +#ifndef TRY_HIGH_FIRST + #define TRY_HIGH_FIRST 0 +#endif + +#ifndef K8_HT_FREQ_1G_SUPPORT + #define K8_HT_FREQ_1G_SUPPORT 0 +#endif + +#ifndef K8_HT_CHECK_PENDING_LINK + #if CONFIG_MAX_PHYSICAL_CPUS >= 4 + #define K8_HT_CHECK_PENDING_LINK 1 + #else + #define K8_HT_CHECK_PENDING_LINK 0 + #endif +#endif + +#ifndef CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED + #define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0 +#endif + +#ifndef ENABLE_APIC_EXT_ID + #define ENABLE_APIC_EXT_ID 0 +#endif + + +static inline void print_linkn (const char *strval, uint8_t byteval) +{ +#if 1 +#if CONFIG_USE_INIT + printk_debug("%s%02x\r\n", strval, byteval); +#else + print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n"); +#endif +#endif +} + +static void disable_probes(void) +{ + /* disable read/write/fill probes for uniprocessor setup + * they don't make sense if only one cpu is available + */ + + /* Hypetransport Transaction Control Register + * F0:0x68 + * [ 0: 0] Disable read byte probe + * 0 = Probes issues + * 1 = Probes not issued + * [ 1: 1] Disable Read Doubleword probe + * 0 = Probes issued + * 1 = Probes not issued + * [ 2: 2] Disable write byte probes + * 0 = Probes issued + * 1 = Probes not issued + * [ 3: 3] Disable Write Doubleword Probes + * 0 = Probes issued + * 1 = Probes not issued. + * [10:10] Disable Fill Probe + * 0 = Probes issued for cache fills + * 1 = Probes not issued for cache fills. + */ + + u32 val; + + print_spew("Disabling read/write/fill probes for UP... "); + + val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); + val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C | + HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | + HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; + pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val); + + print_spew("done.\r\n"); + +} + +static void enable_apic_ext_id(u8 node) +{ +#if ENABLE_APIC_EXT_ID==1 +#warning "FIXME Is the right place to enable apic ext id here?" + + u32 val; + + val = pci_read_config32(NODE_HT(node), 0x68); + val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); + pci_write_config32(NODE_HT(node), 0x68, val); +#endif +} + +static void enable_routing(u8 node) +{ + u32 val; + + /* HT Initialization Control Register + * F0:0x6C + * [ 0: 0] Routing Table Disable + * 0 = Packets are routed according to routing tables + * 1 = Packets are routed according to the default link field + * [ 1: 1] Request Disable (BSP should clear this) + * 0 = Request packets may be generated + * 1 = Request packets may not be generated. + * [ 3: 2] Default Link (Read-only) + * 00 = LDT0 + * 01 = LDT1 + * 10 = LDT2 + * 11 = CPU on same node + * [ 4: 4] Cold Reset + * - Scratch bit cleared by a cold reset + * [ 5: 5] BIOS Reset Detect + * - Scratch bit cleared by a cold reset + * [ 6: 6] INIT Detect + * - Scratch bit cleared by a warm or cold reset not by an INIT + * + */ + + /* Enable routing table */ + print_spew("Enabling routing table for node "); + print_spew_hex8(node); + + val=pci_read_config32(NODE_HT(node), 0x6c); + val &= ~((1<<1)|(1<<0)); + pci_write_config32(NODE_HT(node), 0x6c, val); + + print_spew(" done.\r\n"); +} + +static void fill_row(u8 node, u8 row, u32 value) +{ + pci_write_config32(NODE_HT(node), 0x40+(row<<2), value); +} + +#if CONFIG_MAX_PHYSICAL_CPUS > 1 +static u8 link_to_register(int ldt) +{ + /* + * [ 0: 3] Request Route + * [0] Route to this node + * [1] Route to Link 0 + * [2] Route to Link 1 + * [3] Route to Link 2 + */ + + if (ldt&0x08) return 0x40; + if (ldt&0x04) return 0x20; + if (ldt&0x02) return 0x00; + + /* we should never get here */ + print_spew("Unknown Link\n"); + return 0; +} + +static u32 get_row(u8 node, u8 row) +{ + return pci_read_config32(NODE_HT(node), 0x40+(row<<2)); +} + +static int link_connection(u8 src, u8 dest) +{ + return get_row(src, dest) & 0x0f; +} + +static void rename_temp_node(u8 node) +{ + uint32_t val; + + print_spew("Renaming current temporary node to "); + print_spew_hex8(node); + + val=pci_read_config32(NODE_HT(7), 0x60); + val &= (~7); /* clear low bits. */ + val |= node; /* new node */ + pci_write_config32(NODE_HT(7), 0x60, val); + + print_spew(" done.\r\n"); +} + +static int verify_connection(u8 dest) +{ + /* See if we have a valid connection to dest */ + u32 val; + + /* Verify that the coherent hypertransport link is + * established and actually working by reading the + * remode node's vendor/device id + */ + val = pci_read_config32(NODE_HT(dest),0); + if(val != 0x11001022) + return 0; + + return 1; +} + +static uint16_t read_freq_cap(device_t dev, uint8_t pos) +{ + /* Handle bugs in valid hypertransport frequency reporting */ + uint16_t freq_cap; + uint32_t id; + + freq_cap = pci_read_config16(dev, pos); + freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ + +#if K8_HT_FREQ_1G_SUPPORT == 1 + if (!is_cpu_pre_e0()) + { + return freq_cap; + } +#endif + + id = pci_read_config32(dev, 0); + + /* AMD K8 Unsupported 1Ghz? */ + if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { + freq_cap &= ~(1 << HT_FREQ_1000Mhz); + } + + return freq_cap; +} + +static int optimize_connection(device_t node1, uint8_t link1, device_t node2, uint8_t link2) +{ + static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; + static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; + uint16_t freq_cap1, freq_cap2; + uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2; + uint8_t freq, old_freq; + int needs_reset; + /* Set link width and frequency */ + + /* Initially assume everything is already optimized and I don't need a reset */ + needs_reset = 0; + + /* Get the frequency capabilities */ + freq_cap1 = read_freq_cap(node1, link1 + PCI_HT_CAP_HOST_FREQ_CAP); + freq_cap2 = read_freq_cap(node2, link2 + PCI_HT_CAP_HOST_FREQ_CAP); + + /* Calculate the highest possible frequency */ + freq = log2(freq_cap1 & freq_cap2); + + /* See if I am changing the link freqency */ + old_freq = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ); + old_freq &= 0x0f; + needs_reset |= old_freq != freq; + old_freq = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ); + old_freq &= 0x0f; + needs_reset |= old_freq != freq; + + /* Set the Calulcated link frequency */ + pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ, freq); + pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ, freq); + + /* Get the width capabilities */ + width_cap1 = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH); + width_cap2 = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH); + + /* Calculate node1's input width */ + ln_width1 = link_width_to_pow2[width_cap1 & 7]; + ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7]; + if (ln_width1 > ln_width2) { + ln_width1 = ln_width2; + } + width = pow2_to_link_width[ln_width1]; + /* Calculate node1's output width */ + ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7]; + ln_width2 = link_width_to_pow2[width_cap2 & 7]; + if (ln_width1 > ln_width2) { + ln_width1 = ln_width2; + } + width |= pow2_to_link_width[ln_width1] << 4; + + /* See if I am changing node1's width */ + old_width = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1); + old_width &= 0x77; + needs_reset |= old_width != width; + + /* Set node1's widths */ + pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1, width); + + // * Calculate node2's width */ + width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); + + /* See if I am changing node2's width */ + old_width = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1); + old_width &= 0x77; + needs_reset |= old_width != width; + + /* Set node2's widths */ + pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1, width); + + return needs_reset; +} + +static uint8_t get_linkn_first(uint8_t byte) +{ + if(byte & 0x02) { byte = 0; } + else if(byte & 0x04) { byte = 1; } + else if(byte & 0x08) { byte = 2; } + return byte; +} + +static uint8_t get_linkn_last(uint8_t byte) +{ + if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; } + if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; } + if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; } + return byte>>4; +} + +static uint8_t get_linkn_last_count(uint8_t byte) +{ + byte &= 0x0f; + if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; } + if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; } + if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; } + return byte>>4; +} + +static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/ +{ + uint8_t linkn; + uint32_t val; + val = 1; + for(linkn = 0; linkn<3; linkn++) { + uint8_t regpos; + uint32_t reg; + regpos = 0x98 + 0x20 * linkn; + reg = pci_read_config32(NODE_HT(source), regpos); + if ((reg & 0x17) != 3) continue; /* it is not conherent or not connected*/ + val |= 1<<(linkn+1); + } + val <<= 16; + val |= 0x0101; + fill_row(source,row, val); +} + +static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn) +{ + uint32_t val; + uint32_t val_s; + val = 1<<(linkn+1); + val |= 1<<(linkn+1+8); /*for direct connect response route should equal to request table*/ + + if(((source &1)!=(dest &1)) +#if CROSS_BAR_47_56 + && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here + //(6,5) (7,4) should be here +#endif + ){ + val |= (1<<16); + } else { + /*for CROSS_BAR_47_56 47, 56, should be here too + and for 47, 56, 57, 75, 46, 64 we need to substract another link to + 6, 7, 6, 6, 7, 7 + */ + val_s = get_row(temp, source); + val |= ((val_s>>16) - (1<<(linkn+1)))<<16; + } + + fill_row(temp,dest, val ); +} + +#if CROSS_BAR_47_56 +static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) { + uint32_t val; + val = get_row(source, dest); + val -= link_connection(source, kickout)<<16; + fill_row(source, dest, val); +} + +static void opt_broadcast_rt_group(const u8 *conn, int num) { + int i; + + for(i=0; i 1*/ + + +#if CONFIG_MAX_PHYSICAL_CPUS > 2 +#if !CROSS_BAR_47_56 +static void setup_row_indirect_x(u8 temp, u8 source, u8 dest) +#else +static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 diff) +#endif +{ + /*for indirect connection, we need to compute the val from val_s(source, source), and val_g(source, gateway) */ + uint32_t val_s; + uint32_t val; +#if !CROSS_BAR_47_56 + u8 gateway; + u8 diff; + if(source>= 16; + val_s &= 0xfe; + +#if !CROSS_BAR_47_56 + diff = ((source&1)!=(dest &1)); +#endif + + if(diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/ + val_s -= val & 0xff; +#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) + uint8_t byte; + /* Some node have two links left + * don't worry we only have (2, (3 as source need to handle + */ + byte = val_s; + byte = get_linkn_last_count(byte); + if((byte>>2)>1) { /* make sure not the corner*/ + if(source>16) - link_connection(temp, gateway))<<16; + } + + fill_row(temp, dest, val); + +} + +#if !CROSS_BAR_47_56 +static void setup_row_indirect(u8 source, u8 dest) +{ + setup_row_indirect_x(source, source, dest); +} +#else +static void setup_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff) +{ + setup_row_indirect_x(source, source, dest, gateway, diff); +} +#endif + +static void setup_row_indirect_group(const u8 *conn, int num) +{ + int i; + +#if !CROSS_BAR_47_56 + for(i=0; i 2*/ + + +static void setup_uniprocessor(void) +{ + print_spew("Enabling UP settings\r\n"); +#if CONFIG_LOGICAL_CPUS==1 + unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; + if (tmp>0) return; +#endif + disable_probes(); +} + +#if CONFIG_MAX_PHYSICAL_CPUS > 2 +static int optimize_connection_group(const u8 *opt_conn, int num) { + int needs_reset = 0; + int i; + for(i=0; i 1 +static unsigned setup_smp2(void) +{ + unsigned nodes; + u8 byte; + uint32_t val; + nodes = 2; + + setup_row_local(0, 0); /* it will update the broadcast RT*/ + + val = get_row(0,0); + byte = (val>>16) & 0xfe; + if(byte<0x2) { /* no coherent connection so get out.*/ + nodes = 1; + return nodes; + } + + /* Setup and check a temporary connection to node 1 */ +#if TRY_HIGH_FIRST == 1 + byte = get_linkn_last(byte); /* Max Link to node1 */ +#else + byte = get_linkn_first(byte); /*Min Link to node1 --- according to AMD*/ +#endif + print_linkn("(0,1) link=", byte); + setup_row_direct(0,1, byte); + setup_temp_row(0, 1); + + verify_connection(7); + + /* We found 2 nodes so far */ + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /*get default link on node7 to node0*/ + print_linkn("(1,0) link=", byte); + setup_row_local(7,1); + setup_remote_row_direct(1, 0, byte); + +#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) + val = get_row(7,1); + byte = (val>>16) & 0xfe; + byte = get_linkn_last_count(byte); + if((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/ + val = get_row(0,0); + byte = (val>>16) & 0xfe; +#if TRY_HIGH_FIRST == 1 + byte = get_linkn_first(byte); /* Min link to Node1 */ +#else + byte = get_linkn_last(byte); /* Max link to Node1*/ +#endif + print_linkn("\t-->(0,1) link=", byte); + setup_row_direct(0,1, byte); + setup_temp_row(0, 1); + + verify_connection(7); + + /* We found 2 nodes so far */ + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on node7 to node0*/ + print_linkn("\t-->(1,0) link=", byte); + setup_row_local(7,1); + setup_remote_row_direct(1, 0, byte); + } +#endif + + setup_remote_node(1); /* Setup the regs on the remote node */ + rename_temp_node(1); /* Rename Node 7 to Node 1 */ + enable_routing(1); /* Enable routing on Node 1 */ +#if 0 + /*don't need and it is done by clear_dead_links */ + clear_temp_row(0); +#endif + + return nodes; +} +#endif /*CONFIG_MAX_PHYSICAL_CPUS > 1 */ + +#if CONFIG_MAX_PHYSICAL_CPUS > 2 + +static unsigned setup_smp4(void) +{ + unsigned nodes; + u8 byte; + uint32_t val; + + nodes=4; + + /* Setup and check temporary connection from Node 0 to Node 2 */ + val = get_row(0,0); + byte = ((val>>16) & 0xfe) - link_connection(0,1); + byte = get_linkn_last_count(byte); + + if((byte>>2)==0) { /* We should have two coherent for 4p and above*/ + nodes = 2; + return nodes; + } + + byte &= 3; /* bit [3,2] is count-1*/ + print_linkn("(0,2) link=", byte); + setup_row_direct(0, 2, byte); /*(0,2) direct link done*/ + + /* We found 3 nodes so far. Now setup a temporary + * connection from node 0 to node 3 via node 1 + */ + setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ + /* here should setup_row_direct(1,3) at first, before that we should find the link in node 1 to 3*/ + val = get_row(1,1); + byte = ((val>>16) & 0xfe) - link_connection(1,0); + byte = get_linkn_first(byte); + print_linkn("(1,3) link=", byte); + setup_row_direct(1,3,byte); /* (1, 3) direct link done*/ + + /* We found 4 nodes so far. Now setup all nodes for 4p */ + // We need to make sure 0,2 and 1,3 link is set already +#if !CROSS_BAR_47_56 + static const u8 conn4_1[] = { + 0,3, + 1,2, + }; +#else + static const u8 conn4_1[] = { + 0,3,2,1, + 1,2,3,1, + }; +#endif + + setup_row_indirect_group(conn4_1, sizeof(conn4_1)/sizeof(conn4_1[0])); + + setup_temp_row(0,2); + verify_connection(7); + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 0*/ + print_linkn("(2,0) link=", byte); + + setup_row_local(7,2); + setup_remote_row_direct(2, 0, byte); /* node 2 to node 0 direct link done */ + setup_remote_node(2); /* Setup the regs on the remote node */ + + rename_temp_node(2); /* Rename Node 7 to Node 2 */ + enable_routing(2); /* Enable routing on Node 2 */ + + setup_temp_row(0,1); + setup_temp_row(1,3); + verify_connection(7); + + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 1*/ + print_linkn("(3,1) link=", byte); + + setup_row_local(7,3); + setup_remote_row_direct(3, 1, byte); /* node 3 to node 1 direct link done */ + setup_remote_node(3); /* Setup the regs on the remote node */ + + /* We need to init link between 2, and 3 direct link */ + val = get_row(2,2); + byte = ((val>>16) & 0xfe) - link_connection(2,0); + byte = get_linkn_last_count(byte); + print_linkn("(2,3) link=", byte & 3); + + setup_row_direct(2,3, byte & 0x3); + setup_temp_row(0,2); + setup_temp_row(2,3); + verify_connection(7); /* to 3*/ + +#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) + /* We need to find out which link is to node3 */ + if((byte>>2)==2) { /* one to node3, one to node0, one to node4*/ + val = get_row(7,3); + if((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/ + val = get_row(2,2); + byte = ((val>>16) & 0xfe) - link_connection(2,0); + byte = get_linkn_first(byte); + print_linkn("\t-->(2,3) link=", byte); + setup_row_direct(2,3,byte); + setup_temp_row(2,3); + verify_connection(7); /* to 3*/ + } + } +#endif + + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 2*/ + print_linkn("(3,2) link=", byte); + setup_remote_row_direct(3,2, byte); + +#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) + /* set link from 3 to 5 before enable it*/ + val = get_row(7,3); + byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1); + byte = get_linkn_last_count(byte); + if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/ + byte &= 3; /*bit [3,2] is count-2*/ + print_linkn("(3,5) link=", byte); + setup_remote_row_direct(3, 5, byte); + } + + val = get_row(2,2); + byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); + byte = get_linkn_last_count(byte); + + if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/ + byte &= 3; /* bit [3,2] is count-2*/ + print_linkn("(2,4) link=", byte); + setup_row_direct(2, 4, byte); + } +#endif + + //Beside 3, 1 is set, We need to make sure 3, 5 is set already in case has three link in 3 +#if !CROSS_BAR_47_56 + static const u8 conn4_3[] = { + 3,0, + }; +#else + static const u8 conn4_3[] = { + 3,0,1,1, + }; +#endif + setup_remote_row_indirect_group(conn4_3, sizeof(conn4_3)/sizeof(conn4_3[0])); + +/* ready to enable RT for Node 3 */ + rename_temp_node(3); + enable_routing(3); /* enable routing on node 3 (temp.) */ + + // beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2 +#if !CROSS_BAR_47_56 + static const u8 conn4_2[] = { + 2,1, + }; +#else + static const u8 conn4_2[] = { + 2,1,0,1, + }; +#endif + setup_row_indirect_group(conn4_2, sizeof(conn4_2)/sizeof(conn4_2[0])); + +#if 0 + /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */ + /* it will be done by clear_dead_links */ + clear_temp_row(0); + clear_temp_row(1); +#endif + + return nodes; + +} + +#endif /* CONFIG_MAX_PHYSICAL_CPUS > 2 */ + +#if CONFIG_MAX_PHYSICAL_CPUS > 4 + +static unsigned setup_smp6(void) +{ + unsigned nodes; + u8 byte; + uint32_t val; + + nodes=6; + + /* Setup and check temporary connection from Node 0 to Node 4 through 2*/ + val = get_row(2,2); + byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); + byte = get_linkn_last_count(byte); + + if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/ + nodes = 4; + return nodes; + } + + /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3*/ + /* set link from 3 to 5 before enable it*/ + val = get_row(3,3); + byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1); + byte = get_linkn_last_count(byte); + if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/ + nodes = 4; + return nodes; + } + + /* We found 6 nodes so far. Now setup all nodes for 6p */ +#warning "FIXME we need to find out the correct gateway for 6p" + static const u8 conn6_1[] = { +#if !CROSS_BAR_47_56 + 0, 4, + 0, 5, + 1, 4, + 1, 5, + 2, 5, + 3, 4, +#else + 0, 4, 2, 0, + 0, 5, 2, 1, + 1, 4, 3, 1, + 1, 5, 3, 0, + 2, 5, 3, 0, + 3, 4, 2, 0, +#endif + }; + + setup_row_indirect_group(conn6_1, sizeof(conn6_1)/sizeof(conn6_1[0])); + + for(byte=0; byte<4; byte+=2) { + setup_temp_row(byte,byte+2); + } + verify_connection(7); + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /*get default link on 7 to 2*/ + print_linkn("(4,2) link=", byte); + + setup_row_local(7,4); + setup_remote_row_direct(4, 2, byte); + setup_remote_node(4); /* Setup the regs on the remote node */ + + /* Set indirect connection to 0, to 3 */ + //we only need to set 4,0 here + static const u8 conn6_2[] = { +#if !CROSS_BAR_47_56 + 4, 0, +#else + 4, 0, 2, 0, +#endif + }; + + setup_remote_row_indirect_group(conn6_2, sizeof(conn6_2)/sizeof(conn6_2[0])); + + rename_temp_node(4); + enable_routing(4); + + setup_temp_row(0,1); + for(byte=0; byte<4; byte+=2) { + setup_temp_row(byte+1,byte+3); + } + verify_connection(7); + + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 3*/ + print_linkn("(5,3) link=", byte); + setup_row_local(7,5); + setup_remote_row_direct(5, 3, byte); + setup_remote_node(5); /* Setup the regs on the remote node */ + +#if !CROSS_BAR_47_56 + /* We need to init link between 4, and 5 direct link */ + val = get_row(4,4); + byte = ((val>>16) & 0xfe) - link_connection(4,2); + byte = get_linkn_last_count(byte); + print_linkn("(4,5) link=", byte & 3); + + setup_row_direct(4,5, byte & 0x3); + setup_temp_row(0,2); + setup_temp_row(2,4); + setup_temp_row(4,5); + verify_connection(7); /* to 5*/ + +#if CONFIG_MAX_PHYSICAL_CPUS > 6 + /* We need to find out which link is to node5 */ + + if((byte>>2)==2) { /* one to node5, one to node2, one to node6*/ + val = get_row(7,5); + if((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/ + val = get_row(4,4); + byte = ((val>>16) & 0xfe) - link_connection(4,2); + byte = get_linkn_first(byte); + print_linkn("\t-->(4,5) link=", byte); + setup_row_direct(4,5,byte); + setup_temp_row(4,5); + verify_connection(7); /* to 5*/ + } + } +#endif + + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ + print_linkn("(5,4) link=", byte); + setup_remote_row_direct(5,4, byte); + + //init 5, 7 here + val = get_row(7,5); + byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3); + byte = get_linkn_last_count(byte); + if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/ + byte &= 3; /*bit [3,2] is count-2*/ + print_linkn("(5,7) link=", byte); + setup_remote_row_direct(5, 7, byte); + } + + //init 4,6 here + val = get_row(4,4); + byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); + byte = get_linkn_last_count(byte); + + if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/ + byte &= 3; /* bit [3,2] is count-2*/ + print_linkn("(4,6) link=", byte); + setup_row_direct(4, 6, byte); + } + +#endif + + //We need to set 5,0 here only, We need to set up 5, 7 to make 5,0 + /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */ + static const u8 conn6_3[] = { +#if !CROSS_BAR_47_56 + 5, 0, +#else + 5, 0, 3, 0, +#endif + }; + + setup_remote_row_indirect_group(conn6_3, sizeof(conn6_3)/sizeof(conn6_3[0])); + +/* ready to enable RT for 5 */ + rename_temp_node(5); + enable_routing(5); /* enable routing on node 5 (temp.) */ + + static const u8 conn6_4[] = { +#if !CROSS_BAR_47_56 + 4, 1, + 4, 3, + + 5, 2, + 5, 1, + +#else + 4, 1, 2, 0, + 4, 3, 2, 0, + 4, 5, 2, 0, + + 5, 2, 3, 0, + 5, 1, 3, 0, + 5, 4, 3, 0, + +#endif + }; + + setup_row_indirect_group(conn6_4, sizeof(conn6_4)/sizeof(conn6_4[0])); + +#if 0 + /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) + * It will be done by clear_dead_links + */ + for(byte=0; byte<4; byte++) { + clear_temp_row(byte); + } +#endif + + return nodes; + +} + +#endif /* CONFIG_MAX_PHYSICAL_CPUS > 4 */ + +#if CONFIG_MAX_PHYSICAL_CPUS > 6 + +static unsigned setup_smp8(void) +{ + unsigned nodes; + u8 byte; + uint32_t val; + + nodes=8; + + /* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */ + val = get_row(4,4); +#if CROSS_BAR_47_56 + byte = ((val>>16) & 0xfe) - link_connection(4,2); +#else + byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); + byte = get_linkn_last_count(byte); /* Max link to 6*/ + if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/ + nodes = 6; + return nodes; + } +#endif + +#if CROSS_BAR_47_56 + byte = get_linkn_last_count(byte); /* Max link to 6*/ + if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/ + nodes = 6; + return nodes; + } +#if TRY_HIGH_FIRST == 1 + byte = ((val>>16) & 0xfe) - link_connection(4,2); + byte = get_linkn_first(byte); /*Min link to 6*/ +#else + byte &= 3; /* bit [3,2] is count-1 or 2*/ +#endif + print_linkn("(4,6) link=", byte); + setup_row_direct(4, 6, byte); +#endif + +#if !CROSS_BAR_47_56 + /* Setup and check temporary connection from Node 0 to Node 7 through 1, 3, 5*/ + val = get_row(5,5); + byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3); + byte = get_linkn_last_count(byte); + if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/ + nodes = 6; + return nodes; + } +#endif + + /* We found 8 nodes so far. Now setup all nodes for 8p */ + static const u8 conn8_1[] = { +#if !CROSS_BAR_47_56 + 0, 6, + /*0, 7,*/ + 1, 6, + /*1, 7,*/ + 2, 6, + /*2, 7,*/ + 3, 6, + /*3, 7,*/ + /*4, 7,*/ + 5, 6, +#else + 0, 6, 2, 0, + /*0, 7, 2, 0,*/ + 1, 6, 3, 0, + /*1, 7, 3, 0,*/ + 2, 6, 4, 0, + /*2, 7, 4, 0,*/ + 3, 6, 5, 1, + /*3, 7, 5, 0,*/ +#endif + }; + + setup_row_indirect_group(conn8_1,sizeof(conn8_1)/sizeof(conn8_1[0])); + + for(byte=0; byte<6; byte+=2) { + setup_temp_row(byte,byte+2); + } + verify_connection(7); + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ + print_linkn("(6,4) link=", byte); + + setup_row_local(7,6); + setup_remote_row_direct(6, 4, byte); + setup_remote_node(6); /* Setup the regs on the remote node */ + /* Set indirect connection to 0, to 3 */ +#warning "FIXME we need to find out the correct gateway for 8p" + static const u8 conn8_2[] = { +#if !CROSS_BAR_47_56 + 6, 0, +#else + 6, 0, 4, 0, +#endif + }; + + setup_remote_row_indirect_group(conn8_2, sizeof(conn8_2)/sizeof(conn8_2[0])); + +#if CROSS_BAR_47_56 + //init 5, 6 here + /* here init 5, 6 */ + /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/ + val = get_row(5,5); + byte = ((val>>16) & 0xfe) - link_connection(5,3); +#if TRY_HIGH_FIRST == 1 + byte = get_linkn_first(byte); +#else + byte = get_linkn_last(byte); +#endif + print_linkn("(5,6) link=", byte); + setup_row_direct(5, 6, byte); + + setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ + for(byte=0; byte<4; byte+=2) { + setup_temp_row(byte+1,byte+3); + } + setup_temp_row(5,6); + + verify_connection(7); + + val = get_row(7,6); // to chect it if it is node6 before renaming + if( (val>>16) == 1) { // it is real node 7 so swap it + /* We need to recompute link to 6 */ + val = get_row(5,5); + byte = ((val>>16) & 0xfe) - link_connection(5,3); +#if TRY_HIGH_FIRST == 1 + byte = get_linkn_first(byte); +#else + byte = get_linkn_last(byte); +#endif + print_linkn("\t-->(5,6) link=", byte); + setup_row_direct(5, 6, byte); +#if 0 + setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ + for(byte=0; byte<4; byte+=2) { + setup_temp_row(byte+1,byte+3); + } +#endif + setup_temp_row(5,6); + + verify_connection(7); + } + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ + print_linkn("(6,5) link=", byte); + setup_remote_row_direct(6, 5, byte); + /*Till now 56, 65 done */ +#endif + + rename_temp_node(6); + enable_routing(6); + +#if !CROSS_BAR_47_56 + setup_temp_row(0,1); + for(byte=0; byte<6; byte+=2) { + setup_temp_row(byte+1,byte+3); + } + + verify_connection(7); + + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ + print_linkn("(7,5) link=", byte); + setup_row_local(7,7); + setup_remote_row_direct(7, 5, byte); + +#else + val = get_row(4,4); + byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6); + byte = get_linkn_first(byte); + print_linkn("(4,7) link=", byte); + setup_row_direct(4, 7, byte); + + /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/ + for(byte=0; byte<4; byte+=2) { + setup_temp_row(byte,byte+2); + } + + verify_connection(7); + + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ + print_linkn("(7,4) link=", byte); + setup_row_local(7,7); + setup_remote_row_direct(7, 4, byte); + /* till now 4-7, 7-4 done. */ +#endif + setup_remote_node(7); /* Setup the regs on the remote node */ + +#if CROSS_BAR_47_56 + /* here init 5, 7 */ + /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/ + val = get_row(5,5); + byte = ((val>>16) & 0xfe) - link_connection(5,3) - link_connection(5,6); + byte = get_linkn_first(byte); + print_linkn("(5,7) link=", byte); + setup_row_direct(5, 7, byte); + + setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ + for(byte=0; byte<4; byte+=2) { + setup_temp_row(byte+1,byte+3); + } + + verify_connection(7); + + val = pci_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ + print_linkn("(7,5) link=", byte); + setup_remote_row_direct(7, 5, byte); + /*Till now 57, 75 done */ + +#endif + + /* We need to init link between 6, and 7 direct link */ + val = get_row(6,6); +#if !CROSS_BAR_47_56 + byte = ((val>>16) & 0xfe) - link_connection(6,4); +#else + byte = ((val>>16) & 0xfe) - link_connection(6,4) - link_connection(6,5); +#endif + byte = get_linkn_first(byte); + print_linkn("(6,7) link=", byte); + setup_row_direct(6,7, byte); + + val = get_row(7,7); +#if !CROSS_BAR_47_56 + byte = ((val>>16) & 0xfe) - link_connection(7,5); +#else + byte = ((val>>16) & 0xfe) - link_connection(7,5) - link_connection(7,4); +#endif + byte = get_linkn_first(byte); + print_linkn("(7,6) link=", byte); + setup_row_direct(7,6, byte); + + /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */ + static const u8 conn8_3[] = { +#if !CROSS_BAR_47_56 + 0, 7, /* restore it*/ + 1, 7, + 2, 7, + 3, 7, + 4, 7, + + 6, 1, + 6, 2, + 6, 3, + 6, 5, + + 7, 0, + 7, 1, + 7, 2, + 7, 3, + 7, 4, +#else + + + 4, 5, 6, 1, + 5, 4, 7, 1, + + 6, 1, 5, 0, // or 4, 1 + 6, 2, 4, 0, + 6, 3, 5, 0, // or 4, 1 + + 7, 0, 4, 0, // or 5, 1 + 7, 1, 5, 0, + 7, 2, 4, 0, // or 5, 1 + 7, 3, 5, 0, + + 0, 7, 2, 0, /* restore it*/ + 1, 7, 3, 0, + 2, 7, 4, 1, + 3, 7, 5, 0, + + 2, 5, 4, 1, /* reset it */ + 3, 4, 5, 1, + + 4, 1, 2, 1, /* reset it */ + 4, 3, 2, 1, + + 5, 2, 3, 1, /* reset it */ + 5, 0, 3, 1, + +#endif + }; + + setup_row_indirect_group(conn8_3, sizeof(conn8_3)/sizeof(conn8_3[0])); + +#if CROSS_BAR_47_56 + /* for 47, 56, 57, 75, 46, 64 we need to substract another link to + 6, 7, 6, 6, 7, 7 */ + static const u8 conn8_4[] = { +//direct + 4, 7, 6, + 5, 6, 7, + 5, 7, 6, + 7, 5, 6, + 4, 6, 7, + 6, 4, 7, + +//in direct + 0, 6, 1, + 0, 7, 1, + + 1, 6, 0, + 1, 7, 0, + + 2, 6, 3, +// 2, 7, 3, + + +// 3, 6, 1, + + 3, 7, 2, + + 6, 0, 7, + 6, 1, 7, // needed for via 5 + 6, 1, 4, // ??? + 6, 2, 7, + 6, 3, 7, // needed for via 5 + 6, 3, 4, //??? + 7, 0, 6, // needed for via 4 + 7, 0, 5, //??? + 7, 1, 6, + 7, 2, 6, // needed for via 4 + 7, 2, 5, //??? + 7, 3, 6, + }; + + opt_broadcast_rt_group(conn8_4, sizeof(conn8_4)/sizeof(conn8_4[0])); + + static const u8 conn8_5[] = { + 2, 7, 0, + + 3, 6, 1, + }; + + opt_broadcast_rt_plus_group(conn8_5, sizeof(conn8_5)/sizeof(conn8_5[0])); +#endif + + + +/* ready to enable RT for Node 7 */ + enable_routing(7); /* enable routing on node 7 (temp.) */ + + return nodes; +} + +#endif /* CONFIG_MAX_PHYSICAL_CPUS > 6 */ + + +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + +static unsigned setup_smp(void) +{ + unsigned nodes; + + print_spew("Enabling SMP settings\r\n"); + + nodes = setup_smp2(); +#if CONFIG_MAX_PHYSICAL_CPUS > 2 + if(nodes == 2) + nodes = setup_smp4(); +#endif + +#if CONFIG_MAX_PHYSICAL_CPUS > 4 + if(nodes == 4) + nodes = setup_smp6(); +#endif + +#if CONFIG_MAX_PHYSICAL_CPUS > 6 + if(nodes == 6) + nodes = setup_smp8(); +#endif + +#if CONFIG_USE_INIT + printk_debug("%02x nodes initialized.\r\n", nodes); +#else + print_debug_hex8(nodes); + print_debug(" nodes initialized.\r\n"); +#endif + + return nodes; +} + +static unsigned verify_mp_capabilities(unsigned nodes) +{ + unsigned node, mask; + + mask = 0x06; /* BigMPCap */ + + for (node=0; node 2 + case 0x02: /* MPCap */ + if(nodes > 2) { + print_err("Going back to DP\r\n"); + return 2; + } + break; +#endif + case 0x00: /* Non SMP */ + if(nodes >1 ) { + print_err("Going back to UP\r\n"); + return 1; + } + break; + } + + return nodes; + +} + + +static void clear_dead_routes(unsigned nodes) +{ + int last_row; + int node, row; +#if CONFIG_MAX_PHYSICAL_CPUS == 8 + if(nodes==8) return;/* don't touch (7,7)*/ +#endif + last_row = nodes; + if (nodes == 1) { + last_row = 0; + } + for(node = 7; node >= 0; node--) { + for(row = 7; row >= last_row; row--) { + fill_row(node, row, DEFAULT); + } + } + + /* Update the local row */ + for( node=0; node> 8) & 0xff)) << 16) | 0x0101); + } +} +#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ + +#if CONFIG_LOGICAL_CPUS==1 +static unsigned verify_dualcore(unsigned nodes) +{ + unsigned node, totalcpus, tmp; + + totalcpus = 0; + for (node=0; node> 12) & 3 ; + totalcpus += (tmp + 1); + } + + return totalcpus; + +} +#endif + +static void coherent_ht_finalize(unsigned nodes) +{ + unsigned node; + int rev_a0; +#if CONFIG_LOGICAL_CPUS==1 + unsigned total_cpus; + + if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ + total_cpus = verify_dualcore(nodes); + } + else { + total_cpus = nodes; + } +#endif + + /* set up cpu count and node count and enable Limit + * Config Space Range for all available CPUs. + * Also clear non coherent hypertransport bus range + * registers on Hammer A0 revision. + */ + + print_spew("coherent_ht_finalize\r\n"); + rev_a0 = is_cpu_rev_a0(); + for (node = 0; node < nodes; node++) { + device_t dev; + uint32_t val; + dev = NODE_HT(node); + + /* Set the Total CPU and Node count in the system */ + val = pci_read_config32(dev, 0x60); + val &= (~0x000F0070); +#if CONFIG_LOGICAL_CPUS==1 + val |= ((total_cpus-1)<<16)|((nodes-1)<<4); +#else + val |= ((nodes-1)<<16)|((nodes-1)<<4); +#endif + pci_write_config32(dev, 0x60, val); + + /* Only respond to real cpu pci configuration cycles + * and optimize the HT settings + */ + val=pci_read_config32(dev, HT_TRANSACTION_CONTROL); + val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) | + (HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) | + (HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT)); + val |= HTTC_LIMIT_CLDT_CFG | + (HTTC_BUF_REL_PRI_8 << HTTC_BUF_REL_PRI_SHIFT) | + (3 << HTTC_MED_PRI_BYP_CNT_SHIFT) | + (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); + pci_write_config32(dev, HT_TRANSACTION_CONTROL, val); + + if (rev_a0) { + pci_write_config32(dev, 0x94, 0); + pci_write_config32(dev, 0xb4, 0); + pci_write_config32(dev, 0xd4, 0); + } + } + + print_spew("done\r\n"); +} + +static int apply_cpu_errata_fixes(unsigned nodes) +{ + unsigned node; + int needs_reset = 0; + for(node = 0; node < nodes; node++) { + device_t dev; + uint32_t cmd; + dev = NODE_MC(node); + if (is_cpu_pre_c0()) { + + /* Errata 66 + * Limit the number of downstream posted requests to 1 + */ + cmd = pci_read_config32(dev, 0x70); + if ((cmd & (3 << 0)) != 2) { + cmd &= ~(3<<0); + cmd |= (2<<0); + pci_write_config32(dev, 0x70, cmd ); + needs_reset = 1; + } + cmd = pci_read_config32(dev, 0x7c); + if ((cmd & (3 << 4)) != 0) { + cmd &= ~(3<<4); + cmd |= (0<<4); + pci_write_config32(dev, 0x7c, cmd ); + needs_reset = 1; + } + /* Clock Power/Timing Low */ + cmd = pci_read_config32(dev, 0xd4); + if (cmd != 0x000D0001) { + cmd = 0x000D0001; + pci_write_config32(dev, 0xd4, cmd); + needs_reset = 1; /* Needed? */ + } + + } + else if (is_cpu_pre_d0()) { // d0 later don't need it + uint32_t cmd_ref; + /* Errata 98 + * Set Clk Ramp Hystersis to 7 + * Clock Power/Timing Low + */ + cmd_ref = 0x04e20707; /* Registered */ + cmd = pci_read_config32(dev, 0xd4); + if(cmd != cmd_ref) { + pci_write_config32(dev, 0xd4, cmd_ref ); + needs_reset = 1; /* Needed? */ + } + } + } + return needs_reset; +} + +static int optimize_link_read_pointers(unsigned nodes) +{ + unsigned node; + int needs_reset = 0; + for(node = 0; node < nodes; node++) { + device_t f0_dev, f3_dev; + uint32_t cmd_ref, cmd; + int link; + f0_dev = NODE_HT(node); + f3_dev = NODE_MC(node); + cmd_ref = cmd = pci_read_config32(f3_dev, 0xdc); + for(link = 0; link < 3; link++) { + uint32_t link_type; + unsigned reg; + /* This works on an Athlon64 because unimplemented links return 0 */ + reg = 0x98 + (link * 0x20); + link_type = pci_read_config32(f0_dev, reg); + /* Only handle coherent links */ + if ((link_type & (LinkConnected | InitComplete|NonCoherent)) == + (LinkConnected|InitComplete)) + { + cmd &= ~(0xff << (link *8)); + cmd |= 0x25 << (link *8); + } + } + if (cmd != cmd_ref) { + pci_write_config32(f3_dev, 0xdc, cmd); + needs_reset = 1; + } + } + return needs_reset; +} + +static int optimize_link_coherent_ht(void) +{ + int needs_reset = 0; + + unsigned nodes; + + nodes = get_nodes(); + +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + if(nodes>1) { + needs_reset |= optimize_connection( + NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)), + NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) ); + } + +#if CONFIG_MAX_PHYSICAL_CPUS > 2 + if(nodes>2) { + /* optimize physical connections - by LYH */ + static const u8 opt_conn4[] = { + 0,2, + 1,3, + 2,3, + }; + needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0])); + } +#endif + +#if CONFIG_MAX_PHYSICAL_CPUS > 4 + if(nodes>4) { + static const uint8_t opt_conn6[] ={ + 2, 4, + 3, 5, + #if !CROSS_BAR_47_56 + 4, 5, + #endif + }; + needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0])); + } +#endif + +#if CONFIG_MAX_PHYSICAL_CPUS > 6 + if(nodes>6) { + static const uint8_t opt_conn8[] ={ + 4, 6, + #if CROSS_BAR_47_56 + 4, 7, + 5, 6, + #endif + 5, 7, + 6, 7, + }; + needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0])); + } +#endif + +#endif + + needs_reset |= apply_cpu_errata_fixes(nodes); + needs_reset |= optimize_link_read_pointers(nodes); + + return needs_reset; +} + +#if RAMINIT_SYSINFO == 1 +static void setup_coherent_ht_domain(void) +#else +static int setup_coherent_ht_domain(void) +#endif +{ + unsigned nodes; + nodes = 1; + + enable_bsp_routing(); + +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + nodes = setup_smp(); + nodes = verify_mp_capabilities(nodes); + clear_dead_routes(nodes); +#endif + + if (nodes == 1) { + setup_uniprocessor(); + } + coherent_ht_finalize(nodes); + +#if RAMINIT_SYSINFO == 0 + return optimize_link_coherent_ht(); +#endif +} + diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 2623935ab2..c04781f2c0 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -968,34 +968,4 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo) #endif -static unsigned get_sblnk(void) -{ - uint32_t reg; - /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); - return ((reg>>8) & 3) ; -} - -/* Look up a which bus a given node/link combination is on. - * return 0 when we can't find the answer. - */ - -static unsigned node_link_to_bus(unsigned node, unsigned link) -{ - unsigned reg; - - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - unsigned config_map; - config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); - if ((config_map & 3) != 3) { - continue; - } - if ((((config_map >> 4) & 7) == node) && - (((config_map >> 8) & 3) == link)) - { - return (config_map >> 16) & 0xff; - } - } - return 0; -} diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index c6a649a883..2141b31843 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -18,6 +18,10 @@ #define K8_4RANK_DIMM_SUPPORT 0 #endif +#if USE_DCACHE_RAM == 1 +static void hard_reset(void); +#endif + #if 1 static void setup_resource_map(const unsigned int *register_values, int max) { diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index e60447c2ff..932b807b45 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -51,3 +51,37 @@ static void set_bios_reset(void) htic &= ~HTIC_BIOSR_Detect; pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); } + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + +static unsigned get_sblk(void) +{ + uint32_t reg; + /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ + reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); + return ((reg>>8) & 3) ; +} + +static unsigned get_sbbusn(unsigned sblk) +{ + return node_link_to_bus(0, sblk); +} + + diff --git a/src/southbridge/amd/amd8111/Config.lb b/src/southbridge/amd/amd8111/Config.lb index a69229260b..dfb7f16a49 100644 --- a/src/southbridge/amd/amd8111/Config.lb +++ b/src/southbridge/amd/amd8111/Config.lb @@ -9,3 +9,4 @@ driver amd8111_ac97.o driver amd8111_nic.o driver amd8111_pci.o driver amd8111_smbus.o +object amd8111_reset.o diff --git a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c index 8a648e8d37..9d40076bea 100644 --- a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c +++ b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c @@ -1,10 +1,31 @@ /* by yhlu 2005.10 */ -static void hard_reset(struct sys_info *sysinfo) +static unsigned get_sbdn(unsigned bus) { device_t dev; - - /* Find the device */ - dev = PCI_DEV(sysinfo->sbbusn, sysinfo->sbdn+1, 3); + + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), + bus); + + return (dev>>15) & 0x1f; + +} + +static void hard_reset(void) +{ + device_t dev; + unsigned bus; + + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + bus = get_sbbusn(get_sblk()); + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ACPI), + bus); set_bios_reset(); @@ -14,11 +35,11 @@ static void hard_reset(struct sys_info *sysinfo) outb(0x0e, 0x0cf9); } -static void enable_fid_change_on_sb(struct sys_info *sysinfo) +static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { device_t dev; - /* Find the device */ - dev = PCI_DEV(sysinfo->sbbusn, sysinfo->sbdn+1, 3); + + dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI pci_write_config8(dev, 0x74, 4); @@ -27,15 +48,25 @@ static void enable_fid_change_on_sb(struct sys_info *sysinfo) } -static void soft_reset(struct sys_info *sysinfo) +static void soft_reset_x(unsigned sbbusn, unsigned sbdn) { device_t dev; - - /* Find the device */ - dev = PCI_DEV(sysinfo->sbbusn, sysinfo->sbdn+1, 0); + dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA + + /* Reset */ set_bios_reset(); pci_write_config8(dev, 0x47, 1); + } +static void soft_reset(void) +{ + unsigned sblk = get_sblk(); + unsigned sbbusn = get_sbbusn(sblk); + unsigned sbdn = get_sbdn(sbbusn); + + return soft_reset_x(sbbusn, sbdn); + +} diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c index 1850d51185..0232c6a3e5 100644 --- a/src/southbridge/amd/amd8111/amd8111_lpc.c +++ b/src/southbridge/amd/amd8111/amd8111_lpc.c @@ -70,10 +70,12 @@ static void setup_ioapic(void) unsigned long ioapic_base = 0xfec00000; volatile unsigned long *l; struct ioapicreg *a = ioapicregvalues; + unsigned long bsp_apicid = lapicid(); l = (unsigned long *) ioapic_base; - ioapicregvalues[0].value_high = lapicid()<<(56-32); + ioapicregvalues[0].value_high = bsp_apicid<<(56-32); + printk_debug("amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); i++, a++) { @@ -88,7 +90,7 @@ static void setup_ioapic(void) return; } printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n", - a->reg, a->value_low, a->value_high); + a->reg, a->value_low, a->value_high); } } @@ -179,7 +181,7 @@ static void amd8111_lpc_enable_resources(device_t dev) static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x70, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/amd8111_reset.c index 435904aabd..8a5f3a5135 100644 --- a/src/southbridge/amd/amd8111/amd8111_reset.c +++ b/src/southbridge/amd/amd8111/amd8111_reset.c @@ -1,5 +1,3 @@ -/* Include this file in the mainboards reset.c - */ #include #include @@ -38,7 +36,7 @@ static unsigned pci_read_config32(device_t dev, unsigned where) } #define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device(unsigned pci_id, unsigned bus) +static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { device_t dev, last; dev = PCI_DEV(bus, 0, 0); @@ -55,35 +53,19 @@ static device_t pci_locate_device(unsigned pci_id, unsigned bus) #include "../../../northbridge/amd/amdk8/reset_test.c" -static unsigned node_link_to_bus(unsigned node, unsigned link) -{ - unsigned reg; - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - unsigned config_map; - config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); - if ((config_map & 3) != 3) { - continue; - } - if ((((config_map >> 4) & 7) == node) && - (((config_map >> 8) & 3) == link)) - { - return (config_map >> 16) & 0xff; - } - } - return 0; -} - -static void amd8111_hard_reset(unsigned node, unsigned link) +void hard_reset(void) { device_t dev; unsigned bus; + unsigned node = 0; + unsigned link = get_sblk(); /* Find the device. * There can only be one 8111 on a hypertransport chain/bus. */ bus = node_link_to_bus(node, link); - dev = pci_locate_device( + dev = pci_locate_device_on_bus( PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), bus); diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c index 7a7e467e72..bd14635541 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_setup.c +++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c @@ -383,3 +383,23 @@ static int ck804_early_setup_x(void) ck804_early_clear_port(); return set_ht_link_ck804(4); } + +static void hard_reset(void) +{ + set_bios_reset(); + + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); +} + +static void soft_reset(void) +{ + set_bios_reset(); +#if 1 + /* link reset */ + outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); +#endif +} + diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c index bc382ca7e3..a144f1227a 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c +++ b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c @@ -426,3 +426,23 @@ static int ck804_early_setup_x(void) ck804_early_clear_port(ck804_num, busn, io_base); return set_ht_link_ck804(4); } + +static void hard_reset(void) +{ + set_bios_reset(); + + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); +} + +static void soft_reset(void) +{ + set_bios_reset(); +#if 1 + /* link reset */ + outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); +#endif +} + diff --git a/src/southbridge/nvidia/ck804/ck804_enable_rom.c b/src/southbridge/nvidia/ck804/ck804_enable_rom.c index 48ce689358..070c09efe3 100644 --- a/src/southbridge/nvidia/ck804/ck804_enable_rom.c +++ b/src/southbridge/nvidia/ck804/ck804_enable_rom.c @@ -3,6 +3,7 @@ * by yhlu@tyan.com */ + static void ck804_enable_rom(void) { unsigned char byte; diff --git a/src/southbridge/nvidia/ck804/ck804_smbus.h b/src/southbridge/nvidia/ck804/ck804_smbus.h index 079007836f..88843585aa 100644 --- a/src/southbridge/nvidia/ck804/ck804_smbus.h +++ b/src/southbridge/nvidia/ck804/ck804_smbus.h @@ -29,14 +29,13 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) unsigned char val; smbus_delay(); val = inb(smbus_io_base + SMBHSTSTAT); - if ((val & 0x1f) == 0) { - break; - } - if(loops == (SMBUS_TIMEOUT / 2)) { - outb((val & 0x1f),smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { + return 0; } + outb(val,smbus_io_base + SMBHSTSTAT); } while(--loops); - return loops?0:-2; + return -2; } static int smbus_wait_until_done(unsigned smbus_io_base) @@ -49,10 +48,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base) val = inb(smbus_io_base + SMBHSTSTAT); if ( (val & 0xff) != 0) { - break; + return 0; } } while(--loops); - return loops?0:-3; + return -3; } static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { @@ -200,3 +199,4 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned } return 0; } + diff --git a/targets/tyan/s2892/Config.lb b/targets/tyan/s2892/Config.lb index 465ad47d98..3afb2732f5 100644 --- a/targets/tyan/s2892/Config.lb +++ b/targets/tyan/s2892/Config.lb @@ -7,8 +7,10 @@ mainboard tyan/s2892 # Tyan s2892 romimage "normal" +# 48K for ATI ROM in 1M + option ROM_SIZE = 999424 # 48K for SCSI FW or ATI ROM - option ROM_SIZE = 475136 +# option ROM_SIZE = 475136 # 48K for SCSI FW and 48K for ATI ROM # option ROM_SIZE = 425984 # 64K for Etherboot diff --git a/targets/tyan/s2895/Config.lb b/targets/tyan/s2895/Config.lb index 2a9b4870cd..54c5a6cad6 100644 --- a/targets/tyan/s2895/Config.lb +++ b/targets/tyan/s2895/Config.lb @@ -29,8 +29,7 @@ romimage "normal" # payload ../../../payloads/filo.zelf # payload ../../../payloads/tg3.zelf # payload ../../../payloads/tg3--filo_hda2_vga.zelf -# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf - payload /tmp/filo.elf + payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf # payload ../../../payloads/forcedeth_vga.zelf # payload ../../../payloads/forcedeth--filo_hda2_vga_5_4.zelf # payload ../../../../../../elf/ram0_2.5_2.6.11.tiny.elf @@ -59,8 +58,7 @@ romimage "fallback" # payload ../../../payloads/filo.zelf # payload ../../../payloads/tg3.zelf # payload ../../../payloads/tg3--filo_hda2_vga.zelf -# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf - payload /tmp/filo.elf + payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf # payload ../../../payloads/forcedeth_vga.zelf # payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf # payload ../../../payloads/tg3_vga.zelf