Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-48
Creator: Ronald G. Minnich <rminnich@lanl.gov> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical)
parent
897c78bd15
commit
9a796d1ffb
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@ -49,38 +49,61 @@
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#define OUTC(addr, val) *(unsigned char *)(addr) = (val)
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/* sadly, romcc can't quite handle what we want, so we do this ugly thing */
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#define drcctl (( volatile unsigned char *)0xfffef010)
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#define drcmctl (( volatile unsigned char *)0xfffef012)
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#define drccfg (( volatile unsigned char *)0xfffef014)
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#define drcbendadr (( volatile unsigned char *)0xfffef018)
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#define eccctl (( volatile unsigned char *)0xfffef020)
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#define dbctl (( volatile unsigned char *)0xfffef040)
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void
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setupsc520(void){
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unsigned char *cp;
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unsigned short *sp;
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unsigned long *edi;
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unsigned long *par;
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volatile unsigned char *cp;
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volatile unsigned short *sp;
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volatile unsigned long *edi;
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volatile unsigned long *par;
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/* do this to see if MMCR will start acting right.
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* we suspect you have to do SOMETHING to get things going.
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* I'm really starting to hate this processor.
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*/
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/* no, that did not help. I wonder what will?
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* outl(0x800df0cb, 0xfffc);
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*/
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/* turn off the write buffer*/
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cp = (unsigned char *)0xfffef040;
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*cp = 0;
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/* byte writes in AMD assembly */
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/* we do short anyway, since u-boot does ... */
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/*set the GP CS offset*/
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cp = (unsigned char *)0xfffefc08;
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*cp = 0x00001;
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sp = (unsigned short *)0xfffefc08;
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*sp = 0x00001;
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/*set the GP CS width*/
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cp = (unsigned char *)0xfffefc09;
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*cp = 0x00003;
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sp = (unsigned short *)0xfffefc09;
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*sp = 0x00003;
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/* short writes in AMD assembly */
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/*set the GP CS width*/
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cp = (unsigned char *)0xfffefc0a;
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*cp = 0x00001;
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sp = (unsigned short *)0xfffefc0a;
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*sp = 0x00001;
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/*set the RD pulse width*/
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cp = (unsigned char *)0xfffefc0b;
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*cp = 0x00003;
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sp = (unsigned short *)0xfffefc0b;
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*sp = 0x00003;
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/*set the GP RD offset */
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cp = (unsigned char *)0xfffefc0c;
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*cp = 0x00001;
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sp = (unsigned short *)0xfffefc0c;
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*sp = 0x00001;
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/*set the GP WR pulse width*/
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cp = (unsigned char *)0xfffefc0d;
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*cp = 0x00003;
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sp = (unsigned short *)0xfffefc0d;
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*sp = 0x00003;
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/*set the GP WR offset*/
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cp = (unsigned char *)0xfffefc0e;
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*cp = 0x00001;
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sp = (unsigned short *)0xfffefc0e;
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*sp = 0x00001;
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/* set up the GP IO pins*/
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/*set the GPIO directionreg*/
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sp = (unsigned short *)0xfffefc2c;
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@ -95,55 +118,17 @@ setupsc520(void){
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sp = (unsigned short *)0xfffefc20;
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*sp = 0x0FFFF;
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#ifdef NETSC520
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if NetSC520
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; set the PIO regs correctly.
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/*set the GPIO16-31 direction reg*/
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sp = (unsigned short *)0xfffefc2c;
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*sp = 0x000ff;
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/*set the PIODIR15_0 direction reg*/
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sp = (unsigned short *)0xfffefc2a;
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*sp = 0x00440;
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/*set the PIOPFS31_16 direction reg*/
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sp = (unsigned short *)0xfffefc22;
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*sp = 0x00600;
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/*set the PIOPFS15_0 direction reg*/
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sp = (unsigned short *)0xfffefc20;
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*sp = 0x0FBBF;
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/*set the PIODATA15_0 reg*/
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sp = (unsigned short *)0x0xfffefc30;
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*sp = 0x0f000;
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/*set the CSPFS reg*/
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sp = (unsigned short *)0xfffefc24;
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*sp = 0x0000;
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; The NetSC520 uses PIOs 16-23 for LEDs instead of port 80
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; output a 1 to the leds
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/*set the GPIO16-31 direction reg*/
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sp = (unsigned short *)0xfffefc32;
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mov al, not 1
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else
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#endif
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/* setup for the CDP*/
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/*set the GPIO directionreg*/
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sp = (unsigned short *)0xfffefc2c;
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*sp = 0x00000;
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/*set the GPIO directionreg*/
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sp = (unsigned short *)0xfffefc2a;
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*sp = 0x00000;
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/*set the GPIO pin function 31-16 reg*/
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sp = (unsigned short *)0xfffefc22;
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*sp = 0x0FFFF;
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/*set the GPIO pin function 15-0 reg*/
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sp = (unsigned short *)0xfffefc20;
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*sp = 0x0FFFF;
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/* the 0x80 led should now be working*/
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outb(0xaa, 0x80);
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/*
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; set up a PAR to allow access to the 680 leds
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; WriteMMCR( 0xc4,0x28000680); // PAR15
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*/
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/* wtf are 680 leds ... */
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par = (unsigned long *) 0xfffef0c4;
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*par = 0x28000680;
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/* well? */
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outb(0x55, 0x80);
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/*; set the uart baud rate clocks to the normal 1.8432 MHz.*/
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cp = (unsigned char *)0xfffefcc0;
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*cp = 4; /* uart 1 clock source */
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@ -182,7 +167,7 @@ else
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/* set up the PAR registers as they are on the MSM586SEG */
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par = (unsigned long *) 0xfffef080;
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par = (unsigned long *) 0xfffef088;
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*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
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*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
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*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
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@ -247,218 +232,31 @@ void sc520_udelay(int microseconds) {
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;
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}
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struct ramctl {
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unsigned char drcctl;
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unsigned char pad1;
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unsigned char drcmctl;
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unsigned char pad2;
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unsigned char drccfg;
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unsigned char pad[3];
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unsigned char drcbendadr[4];
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};
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#define RAMCTL (struct ramctl *) 0xfffef010
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static void dumpram(void){
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struct ramctl *ram = RAMCTL;
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print_err("ctl "); print_err_hex8(ram->drcctl); print_err("\r\n");
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print_err("mctl "); print_err_hex8(ram->drcmctl); print_err("\r\n");
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print_err("cfg "); print_err_hex8(ram->drccfg); print_err("\r\n");
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print_err("ctl "); print_err_hex8(*drcctl); print_err("\r\n");
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print_err("mctl "); print_err_hex8(*drcmctl); print_err("\r\n");
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print_err("cfg "); print_err_hex8(*drccfg); print_err("\r\n");
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print_err("bendadr0 "); print_err_hex8(ram->drcbendadr[0]); print_err("\r\n");
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print_err("bendadr1 "); print_err_hex8(ram->drcbendadr[1]); print_err("\r\n");
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print_err("bendadr2 "); print_err_hex8(ram->drcbendadr[2]); print_err("\r\n");
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print_err("bendadr3"); print_err_hex8(ram->drcbendadr[3]); print_err("\r\n");
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print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\r\n");
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print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\r\n");
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print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\r\n");
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print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\r\n");
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}
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#ifdef FUCK
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struct eccctl {
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unsigned char eccctl;
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unsigned char eccsta;
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unsigned char eccckbpos;
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unsigned char ecccktest;
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unsigned char eccsbadd;
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unsigned char pad[3];
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unsigned char eccmbad;
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};
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#define ECCCTL (struct eccctl *) 0xfffef020
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#define DBCTL (unsigned char *) 0xfffef040
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#if 0
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int nextbank(int bank)
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{
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struct ramctl *ram = RAMCTL;
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struct eccctl *ecc = ECCCTL;
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unsigned char *dbctl = DBCTL;
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int rows,banks, cols, i;
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unsigned char ending_adr;
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/* this is really ugly, it is right from assembly code.
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* we need to clean it up later
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*/
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start:
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/* write col 11 wrap adr */
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COL11_ADR=COL11_DATA;
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if(COL11_ADR!=COL11_DATA)
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goto bad_ram;
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//while(1)
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print_err("11\n");
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/* write col 10 wrap adr */
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COL10_ADR=COL10_DATA;
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if(COL10_ADR!=COL10_DATA)
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goto bad_ram;
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print_err("10\n");
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/* write col 9 wrap adr */
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COL09_ADR=COL09_DATA;
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if(COL09_ADR!=COL09_DATA)
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goto bad_ram;
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print_err("9\n");
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/* write col 8 wrap adr */
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COL08_ADR=COL08_DATA;
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if(COL08_ADR!=COL08_DATA)
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goto bad_ram;
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print_err("8\n");
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/* write row 14 wrap adr */
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ROW14_ADR=ROW14_DATA;
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if(ROW14_ADR!=ROW14_DATA)
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goto bad_ram;
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print_err("14\n");
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/* write row 13 wrap adr */
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ROW13_ADR=ROW13_DATA;
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if(ROW13_ADR!=ROW13_DATA)
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goto bad_ram;
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print_err("13\n");
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/* write row 12 wrap adr */
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ROW12_ADR=ROW12_DATA;
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if(ROW12_ADR!=ROW12_DATA)
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goto bad_ram;
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print_err("12\n");
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/* write row 11 wrap adr */
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ROW11_ADR=ROW11_DATA;
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if(ROW11_ADR!=ROW11_DATA)
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goto bad_ram;
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print_err("11\n");
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/* write row 10 wrap adr */
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ROW10_ADR=ROW10_DATA;
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if(ROW10_ADR!=ROW10_DATA)
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goto bad_ram;
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print_err("10\n");
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/*
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* read data @ row 12 wrap adr to determine # banks,
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* and read data @ row 14 wrap adr to determine # rows.
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* if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
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* if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
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* if data @ row 12 wrap == 11 or 12, we have 4 banks
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*/
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banks=2;
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if (ROW12_ADR != ROW10_DATA) {
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banks=4;
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print_err("4b\n");
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if(ROW12_ADR != ROW11_DATA) {
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if(ROW12_ADR != ROW12_DATA)
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goto bad_ram;
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}
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}
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/* validate row mask */
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rows=ROW14_ADR;
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if (rows<ROW11_DATA)
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goto bad_ram;
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if (rows>ROW14_DATA)
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goto bad_ram;
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/* verify all 4 bytes of dword same */
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if(rows&0xffff!=(rows>>16)&0xffff)
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goto bad_ram;
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if(rows&0xff!=(rows>>8)&0xff)
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goto bad_ram;
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print_err("rows"); print_err_hex32(rows); print_err("\n");
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/* validate column data */
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cols=COL11_ADR;
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if(cols<COL08_DATA)
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goto bad_ram;
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if (cols>COL11_DATA)
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goto bad_ram;
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/* verify all 4 bytes of dword same */
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if(cols&0xffff!=(cols>>16)&0xffff)
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goto bad_ram;
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if(cols&0xff!=(cols>>8)&0xff)
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goto bad_ram;
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print_err("cols"); print_err_hex32(cols); print_err("\n");
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cols -= COL08_DATA;
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i = cols + rows;
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/* wacky end addr calculation */
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/*
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al = 3;
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al -= (i & 0xff);k
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*/
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if(banks==4)
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i+=8; /* <-- i holds merged value */
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/* fix ending addr mask*/
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/*FIXME*/
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/* let's just go with this to start ... see if we can get ANYWHERE */
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ending_adr=0xff;
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bad_reint:
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/* issue all banks recharge */
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ram->drcctl=0x02;
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dummy_write();
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/* update ending address register */
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ram->drcbendadr[bank] = ending_adr;
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/* update config register */
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ram->drccfg = (banks = 4 ? 8 : 0) | cols & 3;
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/* skip the rest for now */
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bank = 0;
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// *drccfg=*drccfg&YYY|ZZZZ;
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if(bank!=0) {
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bank--;
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//*(&*drcbendadr+XXYYXX)=0xff;
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goto start;
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}
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/* set control register to NORMAL mode */
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ram->drcctl=0x00;
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dummy_write();
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return bank;
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bad_ram:
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print_info("bad ram!\r\n");
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}
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#endif
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/* cache is assumed to be disabled */
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int sizemem(void)
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{
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struct ramctl *ram = RAMCTL;
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struct eccctl *ecc = ECCCTL;
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unsigned char *dbctl = DBCTL;
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int rows,banks, cols, i, bank;
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unsigned char ending_adr, al;
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unsigned char al;
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/* initialize dram controller registers */
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*dbctl = 0; /* disable write buffer/read-ahead buffer */
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ecc->eccctl = 0;
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ram->drcmctl = 0x1e; /* Set SDRAM timing for slowest speed. */
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*eccctl = 0;
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*drcmctl = 0x1e; /* Set SDRAM timing for slowest speed. */
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/* setup loop to do 4 external banks starting with bank 3 */
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print_err("sizemem\n");
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@ -466,20 +264,20 @@ int sizemem(void)
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/* enable last bank and setup ending address
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* register for max ram in last bank
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*/
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ram->drcbendadr[3]=0x0ff000000;
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*drcbendadr=0x0ff000000;
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/* setup dram register for all banks
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* with max cols and max banks
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*/
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ram->drccfg=0xbbbb;
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*drccfg=0xbbbb;
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dumpram();
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// dumpram();
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/* issue a NOP to all DRAMs */
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/* Setup DRAM control register with Disable refresh,
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* disable write buffer Test Mode and NOP command select
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*/
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ram->drcctl=0x01;
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*drcctl=0x01;
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/* dummy write for NOP to take effect */
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dummy_write();
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@ -489,24 +287,24 @@ int sizemem(void)
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print_err("after sc520_udelay\r\n");
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/* issue all banks precharge */
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ram->drcctl=0x02;
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*drcctl=0x02;
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print_err("set *drcctl to 2 \r\n");
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dummy_write();
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print_err("PRE\n");
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/* issue 2 auto refreshes to all banks */
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ram->drcctl=0x04;
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*drcctl=0x04;
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dummy_write();
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print_err("AUTO1\n");
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dummy_write();
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print_err("AUTO2\n");
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/* issue LOAD MODE REGISTER command */
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ram->drcctl=0x03;
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*drcctl=0x03;
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dummy_write();
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print_err("LOAD MODE REG\n");
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ram->drcctl=0x04;
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*drcctl=0x04;
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for (i=0; i<8; i++) /* refresh 8 times */{
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dummy_write();
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print_err("dummy write\r\n");
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@ -514,7 +312,7 @@ int sizemem(void)
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print_err("8 dummy writes\n");
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/* set control register to NORMAL mode */
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ram->drcctl=0x00;
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*drcctl=0x00;
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print_err("normal\n");
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print_err("HI done normal\r\n");
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@ -605,11 +403,12 @@ print_err("4b\n");
|
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if (rows>ROW14_DATA)
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goto bad_ram;
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/* verify all 4 bytes of dword same */
|
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/*
|
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if(rows&0xffff!=(rows>>16)&0xffff)
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goto bad_ram;
|
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if(rows&0xff!=(rows>>8)&0xff)
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goto bad_ram;
|
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|
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*/
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/* now just get one of them */
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rows &= 0xff;
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print_err("rows"); print_err_hex32(rows); print_err("\n");
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|
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@ -620,10 +419,12 @@ print_err("4b\n");
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if (cols>COL11_DATA)
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goto bad_ram;
|
||||
/* verify all 4 bytes of dword same */
|
||||
/*
|
||||
if(cols&0xffff!=(cols>>16)&0xffff)
|
||||
goto bad_ram;
|
||||
if(cols&0xff!=(cols>>8)&0xff)
|
||||
goto bad_ram;
|
||||
*/
|
||||
print_err("cols"); print_err_hex32(cols); print_err("\n");
|
||||
cols -= COL08_DATA;
|
||||
|
||||
|
|
@ -650,38 +451,41 @@ print_err("4b\n");
|
|||
/*FIXME*/
|
||||
/* let's just go with this to start ... see if we can get ANYWHERE */
|
||||
/* need to get end addr. Need to do it with the bank in mind. */
|
||||
/*
|
||||
al = 3;
|
||||
al -= i&3;
|
||||
ending_adr = rows >> al;
|
||||
*drcbendaddr = rows >> al;
|
||||
print_err("computed ending_adr = "); print_err_hex8(ending_adr);
|
||||
print_err("\r\n");
|
||||
|
||||
*/
|
||||
bad_reinit:
|
||||
/* issue all banks recharge */
|
||||
ram->drcctl=0x02;
|
||||
*drcctl=0x02;
|
||||
dummy_write();
|
||||
|
||||
/* update ending address register */
|
||||
ram->drcbendadr[bank] = ending_adr;
|
||||
// *drcbendadr = ending_adr;
|
||||
|
||||
/* update config register */
|
||||
ram->drccfg &= ~(0xff << bank*4);
|
||||
*drccfg &= ~(0xff << bank*4);
|
||||
if (ending_adr)
|
||||
ram->drccfg = ((banks = 4 ? 8 : 0) | cols & 3)<< (bank*4);
|
||||
dumpram();
|
||||
*drccfg = ((banks == 4 ? 8 : 0) | cols & 3)<< (bank*4);
|
||||
// dumpram();
|
||||
/* skip the rest for now */
|
||||
// bank = 0;
|
||||
// *drccfg=*drccfg&YYY|ZZZZ;
|
||||
|
||||
if(bank!=0) {
|
||||
bank--;
|
||||
ram->drcbendaddr[bank] = 0xff000000;
|
||||
// drcbendaddr--;
|
||||
*drcbendaddr = 0xff000000;
|
||||
//*(&*drcbendadr+XXYYXX)=0xff;
|
||||
goto start;
|
||||
}
|
||||
|
||||
/* set control register to NORMAL mode */
|
||||
ram->drcctl=0x18;
|
||||
*drcctl=0x18;
|
||||
dummy_write();
|
||||
return bank;
|
||||
|
||||
|
|
@ -693,12 +497,10 @@ bad_ram:
|
|||
*/
|
||||
ending_adr = 0;
|
||||
goto bad_reinit;
|
||||
nextbank(3);
|
||||
while(1)
|
||||
print_err("DONE NEXTBANK\r\n");
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
/* note: based on AMD code, but AMD code is BROKEN AFAIK */
|
||||
|
||||
int
|
||||
|
|
@ -706,7 +508,7 @@ staticmem(void){
|
|||
volatile unsigned char *zero = (unsigned char *) 0;
|
||||
/* set up 0x18 .. **/
|
||||
*drcbendadr = 0x88;
|
||||
*drctmctl = 0x1e;
|
||||
*drcmctl = 0x1e;
|
||||
*drccfg = 0x9;
|
||||
/* nop mode */
|
||||
*drcctl = 0x1;
|
||||
|
|
@ -733,4 +535,6 @@ staticmem(void){
|
|||
*drcctl = 0x18;
|
||||
*zero = 0;
|
||||
print_err("DONE the normal\r\n");
|
||||
*zero = 0xdeadbeef;
|
||||
print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -47,26 +47,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
/*
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{
|
||||
.d0 = PCI_DEV(0, 0, 0),
|
||||
.channel0 = { (0xa<<3)|0, 0 },
|
||||
},
|
||||
};
|
||||
*/
|
||||
|
||||
/*
|
||||
if (bist == 0) {
|
||||
early_mtrr_init();
|
||||
}
|
||||
*/
|
||||
setupsc520();
|
||||
uart_init();
|
||||
console_init();
|
||||
// while(1)
|
||||
print_err("HI THERE!\r\n");
|
||||
sizemem();
|
||||
// sizemem();
|
||||
// staticmem();
|
||||
print_err("STATIC MEM DONE\r\n");
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue