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soutbridge/*/bootblock: Use pci_dev_t over device_t typedef 

Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7193
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Edward O'Callaghan 2014-10-26 10:12:15 +11:00 committed by Nico Huber
parent 169c0df6b8
commit 9a817ef183
19 changed files with 24 additions and 24 deletions
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2
src/southbridge/amd/agesa/hudson/bootblock.c
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@ -33,7 +33,7 @@
static void hudson_enable_rom(void) static void hudson_enable_rom(void)
{ {
u8 reg8; u8 reg8;
device_t dev; pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 3); dev = PCI_DEV(0, 0x14, 3);

2
src/southbridge/amd/amd8111/bootblock.c
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@ -26,7 +26,7 @@
static void amd8111_enable_rom(void) static void amd8111_enable_rom(void)
{ {
u8 byte; u8 byte;
device_t dev; pci_devfn_t dev;
dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_8111_ISA), 0); PCI_DEVICE_ID_AMD_8111_ISA), 0);

2
src/southbridge/amd/cimx/sb700/bootblock.c
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@ -24,7 +24,7 @@ static void sb700_enable_rom(void)
{ {
u32 word; u32 word;
u32 dword; u32 dword;
device_t dev; pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 0x03); dev = PCI_DEV(0, 0x14, 0x03);
/* SB700 LPC Bridge 0:20:3:44h. /* SB700 LPC Bridge 0:20:3:44h.

6
src/southbridge/amd/cimx/sb800/bootblock.c
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@ -23,7 +23,7 @@ static void enable_rom(void)
{ {
u16 word; u16 word;
u32 dword; u32 dword;
device_t dev; pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 0x03); dev = PCI_DEV(0, 0x14, 0x03);
/* SB800 LPC Bridge 0:20:3:44h. /* SB800 LPC Bridge 0:20:3:44h.
@ -57,7 +57,7 @@ static void enable_rom(void)
static void enable_prefetch(void) static void enable_prefetch(void)
{ {
u32 dword; u32 dword;
device_t dev = PCI_DEV(0, 0x14, 0x03); pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
/* Enable PrefetchEnSPIFromHost */ /* Enable PrefetchEnSPIFromHost */
dword = pci_io_read_config32(dev, 0xb8); dword = pci_io_read_config32(dev, 0xb8);
@ -67,7 +67,7 @@ static void enable_prefetch(void)
static void enable_spi_fast_mode(void) static void enable_spi_fast_mode(void)
{ {
u32 dword; u32 dword;
device_t dev = PCI_DEV(0, 0x14, 0x03); pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03);
// set temp MMIO base // set temp MMIO base
volatile u32 *spi_base = (void *)0xa0000000; volatile u32 *spi_base = (void *)0xa0000000;

2
src/southbridge/amd/cimx/sb900/bootblock.c
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@ -23,7 +23,7 @@ static void sb900_enable_rom(void)
{ {
u32 word; u32 word;
u32 dword; u32 dword;
device_t dev; pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 0x03); dev = PCI_DEV(0, 0x14, 0x03);
/* SB900 LPC Bridge 0:20:3:44h. /* SB900 LPC Bridge 0:20:3:44h.

2
src/southbridge/amd/sb600/bootblock.c
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@ -34,7 +34,7 @@
static void sb600_enable_rom(void) static void sb600_enable_rom(void)
{ {
u8 reg8; u8 reg8;
device_t dev; pci_devfn_t dev;
dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
PCI_DEVICE_ID_ATI_SB600_LPC), 0); PCI_DEVICE_ID_ATI_SB600_LPC), 0);

2
src/southbridge/amd/sb700/bootblock.c
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@ -35,7 +35,7 @@
static void sb700_enable_rom(void) static void sb700_enable_rom(void)
{ {
u8 reg8; u8 reg8;
device_t dev; pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 3); dev = PCI_DEV(0, 0x14, 3);

2
src/southbridge/amd/sb800/bootblock.c
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@ -33,7 +33,7 @@
static void sb800_enable_rom(void) static void sb800_enable_rom(void)
{ {
u8 reg8; u8 reg8;
device_t dev; pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 3); dev = PCI_DEV(0, 0x14, 3);

2
src/southbridge/broadcom/bcm5785/bootblock.c
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@ -26,7 +26,7 @@
static void bcm5785_enable_rom(void) static void bcm5785_enable_rom(void)
{ {
u8 byte; u8 byte;
device_t dev; pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS,
PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0);

4
src/southbridge/intel/bd82x6x/bootblock.c
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@ -38,7 +38,7 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void) static void enable_spi_prefetch(void)
{ {
u8 reg8; u8 reg8;
device_t dev; pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0); dev = PCI_DEV(0, 0x1f, 0);
@ -50,7 +50,7 @@ static void enable_spi_prefetch(void)
static void enable_port80_on_lpc(void) static void enable_port80_on_lpc(void)
{ {
device_t dev = PCI_DEV(0, 0x1f, 0); pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
/* Enable port 80 POST on LPC */ /* Enable port 80 POST on LPC */
pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);

4
src/southbridge/intel/fsp_bd82x6x/bootblock.c
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@ -43,7 +43,7 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void) static void enable_spi_prefetch(void)
{ {
u8 reg8; u8 reg8;
device_t dev; pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0); dev = PCI_DEV(0, 0x1f, 0);
@ -55,7 +55,7 @@ static void enable_spi_prefetch(void)
static void enable_port80_on_lpc(void) static void enable_port80_on_lpc(void)
{ {
device_t dev = PCI_DEV(0, 0x1f, 0); pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
/* Enable port 80 POST on LPC */ /* Enable port 80 POST on LPC */
pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);

2
src/southbridge/intel/i82371eb/bootblock.c
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@ -26,7 +26,7 @@
static void i82371eb_enable_rom(void) static void i82371eb_enable_rom(void)
{ {
u16 reg16; u16 reg16;
device_t dev; pci_devfn_t dev;
/* /*
* Note: The Intel 82371AB/EB/MB ISA device can be on different * Note: The Intel 82371AB/EB/MB ISA device can be on different

2
src/southbridge/intel/i82801gx/bootblock.c
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@ -34,7 +34,7 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void) static void enable_spi_prefetch(void)
{ {
u8 reg8; u8 reg8;
device_t dev; pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0); dev = PCI_DEV(0, 0x1f, 0);

2
src/southbridge/intel/i82801ix/bootblock.c
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@ -22,7 +22,7 @@
static void enable_spi_prefetch(void) static void enable_spi_prefetch(void)
{ {
u8 reg8; u8 reg8;
device_t dev; pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0); dev = PCI_DEV(0, 0x1f, 0);

4
src/southbridge/intel/lynxpoint/bootblock.c
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@ -38,7 +38,7 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void) static void enable_spi_prefetch(void)
{ {
u8 reg8; u8 reg8;
device_t dev; pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0); dev = PCI_DEV(0, 0x1f, 0);
@ -51,7 +51,7 @@ static void enable_spi_prefetch(void)
static void map_rcba(void) static void map_rcba(void)
{ {
device_t dev = PCI_DEV(0, 0x1f, 0); pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
} }

2
src/southbridge/nvidia/ck804/bootblock.c
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@ -29,7 +29,7 @@
static void ck804_enable_rom(void) static void ck804_enable_rom(void)
{ {
unsigned char byte; unsigned char byte;
device_t addr; pci_devfn_t addr;
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
/* Locate the ck804 LPC. */ /* Locate the ck804 LPC. */

2
src/southbridge/nvidia/mcp55/bootblock.c
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@ -29,7 +29,7 @@ static void mcp55_enable_rom(void)
{ {
u8 byte; u8 byte;
u16 word; u16 word;
device_t addr; pci_devfn_t addr;
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
#if 0 #if 0

2
src/southbridge/sis/sis966/bootblock.c
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@ -30,7 +30,7 @@
static void sis966_enable_rom(void) static void sis966_enable_rom(void)
{ {
device_t addr; pci_devfn_t addr;
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
addr = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, addr = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS,

2
src/southbridge/via/vt8237r/bootblock.c
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@ -22,7 +22,7 @@
static void bootblock_southbridge_init(void) static void bootblock_southbridge_init(void)
{ {
device_t dev; pci_devfn_t dev;
/* don't walk other busses, HT is not enabled */ /* don't walk other busses, HT is not enabled */
/* ROM decode last 8MB FF800000 - FFFFFFFF on VT8237S/VT8237A */ /* ROM decode last 8MB FF800000 - FFFFFFFF on VT8237S/VT8237A */