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nb/intel/haswell: Use {read,write}32p() 

Change-Id: Ibbefa3d57b17a6a8eb0831eeadf6d629e2765567
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes Haouas 2022-12-03 13:31:38 +01:00 committed by Felix Held
parent a2389ef316
commit 9a83eae71e
2 changed files with 5 additions and 5 deletions
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8
src/northbridge/intel/haswell/early_init.c
View File

@ -169,14 +169,14 @@ static void haswell_setup_iommu(void)
/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
u32 reg32;
reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS));
write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), reg32 | DMAR_LCKDN | L3HIT2PEND_DIS);
reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS);
write32p(GFXVT_BASE_ADDRESS + ARCHDIS, reg32 | DMAR_LCKDN | L3HIT2PEND_DIS);
/* Clear SPCAPCTRL */
reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)) & ~SPCAPCTRL;
reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS) & ~SPCAPCTRL;
/* Set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy config registers */
write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS),
write32p(VTVC0_BASE_ADDRESS + ARCHDIS,
reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV);
}

2
src/northbridge/intel/haswell/romstage.c
View File

@ -47,7 +47,7 @@ void mainboard_romstage_entry(void)
if (CONFIG(INTEL_TXT)) {
printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n");
intel_txt_log_acm_error(read32((void *)TXT_ERROR));
intel_txt_log_acm_error(read32p(TXT_ERROR));
intel_txt_log_spad();