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device & commonlib: Update pci_scan_bus postcodes 

The function pci_scan_bus had 3 post codes in it:
0x24 - beginning
0x25 - middle
0x55 - end

I got rid of the middle postcode and used 0x25 for the code signifying
the end of the function.  I don't think all three are needed.

0x24 & 0x25 postcodes are currently also used in intel cache-as-ram
code.  Those postcodes should be adjusted to avoid conflicting.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Martin Roth 2022-11-03 18:40:10 -06:00 committed by Martin L Roth
parent 898176a24c
commit 9a8667a841
2 changed files with 16 additions and 4 deletions
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14
src/commonlib/include/commonlib/console/post_codes.h
View File

@ -65,6 +65,20 @@
*/
#define POST_ENTRY_C_START 0x13
/**
* \brief Entry into pci_scan_bus
*
* Entered pci_scan_bus()
*/
#define POST_ENTER_PCI_SCAN_BUS 0x24
/**
* \brief Entry into pci_scan_bus
*
* Entered pci_scan_bus()
*/
#define POST_EXIT_PCI_SCAN_BUS 0x25
/**
* \brief Pre-memory init preparation start
*

6
src/device/pci_device.c
View File

@ -1423,7 +1423,7 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
max_devfn=0xff;
}
post_code(0x24);
post_code(POST_ENTER_PCI_SCAN_BUS);
if (pci_bus_only_one_child(bus))
max_devfn = MIN(max_devfn, 0x07);
@ -1464,8 +1464,6 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
}
}
post_code(0x25);
/*
* Warn if any leftover static devices are found.
* There's probably a problem in devicetree.cb.
@ -1516,7 +1514,7 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
* side of any bridges that may be on this bus plus any devices.
* Return how far we've got finding sub-buses.
*/
post_code(0x55);
post_code(POST_EXIT_PCI_SCAN_BUS);
}
typedef enum {