soc/intel/skylake: Enable another VR mailbox command for certain boards
Command List: Send command for PS4 exit fails BUG=chrome-os-partner:52355 BRANCH=glados TEST=Build and boot lars and verify no hang during active idle CQ-DEPEND=CL:*257305 Change-Id: I9ffae71b1a38433ffc48ee7be7e2a13e69ad5b87 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 96f00e2d153f92339c378ce256eb7ce6824e3368 Original-Change-Id: I320ae154f3f7145811b57258ddb61b3beb584273 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/341330 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14688 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -169,6 +169,9 @@ chip soc/intel/skylake
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# PL2 override 25W
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register "tdp_pl2_override" = "25"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -173,6 +173,9 @@ chip soc/intel/skylake
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# PL2 override 25W
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register "tdp_pl2_override" = "25"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -330,9 +330,10 @@ struct soc_intel_skylake_config {
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u8 speed_shift_enable;
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/*
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* Enable VR specific mailbox command
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* When set, an extra VR mailbox command specifically
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* for the MPS IMPV8 VR will be sent.
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* 0 - Don't Send, 1 - Send
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* 000b - Don't Send any VR command
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* 001b - VR command specifically for the MPS IMPV8 VR will be sent
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* 010b - VR specific command sent for PS4 exit issue
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* 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue
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*/
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u8 SendVrMbxCmd;
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/* Statically clock gate 8254 PIT. */
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