GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

soc/intel/skylake: Enable another VR mailbox command for certain boards

Browse source 
Command List:
Send command for PS4 exit fails

BUG=chrome-os-partner:52355
BRANCH=glados
TEST=Build and boot lars and verify no hang during active idle

CQ-DEPEND=CL:*257305

Change-Id: I9ffae71b1a38433ffc48ee7be7e2a13e69ad5b87
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 96f00e2d153f92339c378ce256eb7ce6824e3368
Original-Change-Id: I320ae154f3f7145811b57258ddb61b3beb584273
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/341330
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14688
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Subrata Banik 2016-04-20 14:19:53 +05:30 committed by Patrick Georgi
parent e09b5f2d4f
commit 9a8b67d0af
3 changed files with 10 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/mainboard/google/lars/devicetree.cb
View file

@ -169,6 +169,9 @@ chip soc/intel/skylake
# PL2 override 25W # PL2 override 25W
register "tdp_pl2_override" = "25" register "tdp_pl2_override" = "25"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end

3
src/mainboard/intel/kunimitsu/devicetree.cb
View file

@ -173,6 +173,9 @@ chip soc/intel/skylake
# PL2 override 25W # PL2 override 25W
register "tdp_pl2_override" = "25" register "tdp_pl2_override" = "25"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end

7
src/soc/intel/skylake/chip.h
View file

@ -330,9 +330,10 @@ struct soc_intel_skylake_config {
u8 speed_shift_enable; u8 speed_shift_enable;
/* /*
* Enable VR specific mailbox command * Enable VR specific mailbox command
* When set, an extra VR mailbox command specifically * 000b - Don't Send any VR command
* for the MPS IMPV8 VR will be sent. * 001b - VR command specifically for the MPS IMPV8 VR will be sent
* 0 - Don't Send, 1 - Send * 010b - VR specific command sent for PS4 exit issue
* 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue
*/ */
u8 SendVrMbxCmd; u8 SendVrMbxCmd;
/* Statically clock gate 8254 PIT. */ /* Statically clock gate 8254 PIT. */