vendorcode/intel/fsp/fsp2_0: Add FSP header files for Skylake-SP
Add header files for FSP of Skylake Scalable Processor. These header files are from an Intel SKX-SP FSP engineering build. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: If47f102c2c7979da1196f8c6b315d5be558e786c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <anpetrov@fb.com>
This commit is contained in:
Jonathan Zhang
Patrick Georgi
parent
a1d7db8215
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/** @file
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPUPD_H__
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#define __FSPUPD_H__
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#include <FspEas.h>
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#pragma pack(1)
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#define FSPT_UPD_SIGNATURE 0x545F4450554C4E41 /* 'ANLUPD_T' */
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#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4E41 /* 'ANLUPD_M' */
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#define FSPS_UPD_SIGNATURE 0x535F4450554C4E41 /* 'ANLUPD_S' */
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#pragma pack()
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#endif
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@ -0,0 +1,545 @@
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/** @file
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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|
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||||||
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* Redistributions of source code must retain the above copyright notice, this
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|
list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPMUPD_H__
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#define __FSPMUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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/**
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FSP Header Version Number
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**/
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#define FSP_UPD_VERSION (0x1947)
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#define MAX_CHANNEL 6 /* Maximum Number of Memory Channels */
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#define MAX_DIMM 2 /* Maximum Number of DIMMs per Channel */
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/**
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IIO PCIe Ports
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**/
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typedef enum {
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PORT_0 = 0,
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// IOU2
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PORT_1A,
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PORT_1B,
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PORT_1C,
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PORT_1D,
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// IOU0
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PORT_2A,
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PORT_2B,
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PORT_2C,
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PORT_2D,
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// IOU1
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PORT_3A,
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PORT_3B,
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PORT_3C,
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PORT_3D,
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// MCP0
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PORT_4A,
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PORT_4B,
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PORT_4C,
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PORT_4D,
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// MCP1
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PORT_5A,
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PORT_5B,
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PORT_5C,
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PORT_5D,
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MAX_PORTS
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} PCIE_PORTS;
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/**
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IIO Stacks
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**/
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typedef enum {
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CSTACK = 0,
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PSTACK0,
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PSTACK1,
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PSTACK2,
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PSTACK3,
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PSTACK4,
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MAX_STACKS
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} IIO_STACKS;
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/**
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NTB Per Port Definition
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**/
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typedef enum {
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NTB_PORT_TRANSPARENT = 0,
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NTB_PORT_NTB_NTB
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} NTB_PPD;
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/**
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NTB Upstream/Downstream Configuration
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**/
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typedef enum {
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NTB_XLINK_DSD_USP = 2,
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NTB_XLINK_USD_DSP
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} NTB_XLINK;
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/**
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PCIe Link Speed Selection
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**/
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typedef enum {
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PcieAuto = 0,
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PcieGen1,
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PcieGen2,
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PcieGen3
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} PCIE_LINK_SPEED;
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/**
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GPIO Pad Number
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**/
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typedef UINT32 UPD_GPIO_PAD;
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/**
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UPD_GPIO_CONFIG:
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64 bit struct defining GPIO PAD configuration
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**/
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typedef struct {
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/**
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Pad Mode
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Pad can be set as GPIO or one of its native functions.
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When in native mode setting Direction (except Inversion), OutputState,
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InterruptConfig and Host Software Pad Ownership are unnecessary.
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Refer to definition of GPIO_PAD_MODE.
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Refer to EDS for each native mode according to the pad.
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**/
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UINT32 PadMode : 4;
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/**
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Host Software Pad Ownership
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Set pad to ACPI mode or GPIO Driver Mode.
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Refer to definition of GPIO_HOSTSW_OWN.
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**/
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UINT32 HostSoftPadOwn : 2;
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/**
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GPIO Direction
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Can choose between In, In with inversion Out, both In and Out,
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both In with inversion and out or disabling both.
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Refer to definition of GPIO_DIRECTION for supported settings.
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**/
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UINT32 Direction : 5;
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/**
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Output State
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Set Pad output value.
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Refer to definition of GPIO_OUTPUT_STATE for supported settings.
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This setting takes place when output is enabled.
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**/
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UINT32 OutputState : 2;
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/**
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GPIO Interrupt Configuration
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Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting
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is applicable only if GPIO is in input mode.
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If GPIO is set to cause an SCI then also Gpe is enabled for this pad.
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Refer to definition of GPIO_INT_CONFIG for supported settings.
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**/
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UINT32 InterruptConfig : 8;
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/**
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GPIO Power Configuration.
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This setting controls Pad Reset Configuration.
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Refer to definition of GPIO_RESET_CONFIG for supported settings.
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**/
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UINT32 PowerConfig : 4;
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/**
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GPIO Electrical Configuration
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This setting controls pads termination and voltage tolerance.
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Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
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**/
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UINT32 ElectricalConfig : 7;
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/**
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GPIO Lock Configuration
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This setting controls pads lock.
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Refer to definition of GPIO_LOCK_CONFIG for supported settings.
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**/
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UINT32 LockConfig : 3;
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/**
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Additional GPIO configuration
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Refer to definition of GPIO_OTHER_CONFIG for supported settings.
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**/
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UINT32 OtherSettings : 2;
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UINT32 RsvdBits : 27; ///< Reserved bits for future extension
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UINT32 RsvdBits1; ///< Reserved bits for future extension
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} UPD_GPIO_CONFIG;
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/**
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UPD_GPIO_INIT_CONFIG:
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Defines a GPIO Pad and its respective configuration
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Constitutes one entry in the GPIO config table
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Reference FSP implementation:
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AndersonLakePlatPkg\Uba\UbaMain\Pei\TypeAndersonCreek\GpioTable.c
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Bootloaders can include the following to define GPIO PADs/other macros:
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PurleySktPkg\SouthClusterLbg\Include\Library\GpioLib.h
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**/
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typedef struct {
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UPD_GPIO_PAD GpioPad;
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UPD_GPIO_CONFIG GpioConfig;
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} UPD_GPIO_INIT_CONFIG;
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/**
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GPIOTABLE_CONFIG:
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GpioTable - Base Address of the Gpio Table declared by the
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bootloader.
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Default: NULL
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NumberofEntries - Number of Entries in the GPIO Table provided
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Default: 0
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If GpioTable is Null or NumberofEntries is 0, then FSP will handle Gpio Pad
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configuration using default GPIO_INIT_CONFIG tables
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**/
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typedef struct {
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UPD_GPIO_INIT_CONFIG *GpioTable;
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UINT32 NumberOfEntries;
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} GPIOTABLE_CONFIG;
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/**
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UPD_IIO_BIFURCATION_DATA_ENTRY:
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Defines IIO Bifurcation for IIO Units
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Constitutes one entry in the IIO Bifurcation table, describing bifurcation entries as:
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Socket | IOU | Bifurcation
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Valid IouNumbers are from 0 to 4
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Reference FSP Implementation :
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AndersonLakePlatPkg\Uba\UbaMain\Pei\TypeAndersonCreek\IioBifurInit.c
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Definitions for relevant bifurcation macros:
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NumberCpRcPkg\Library\BaseMemoryCoreLib\Chip\Skx\Include\Iio\IioRegs.h
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**/
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typedef struct {
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UINT8 Socket;
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UINT8 IouNumber;
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UINT8 Bifurcation;
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} UPD_IIO_BIFURCATION_DATA_ENTRY;
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/**
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IIOBIFURCATION_CONFIG:
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IIoBifurcationTable - Base Address of the IIO Bifurcation table
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declared by the bootloader
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Default: NULL
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NumberofEntries - Number of Entries in the IIO Bifurcation Table
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Default: 0
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If IIoBifurcationTable is Null or NumberofEntries is 0, then FSP will handle IIO
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bifurcation using default IIO_BIFURCATION_DATA_ENTRY tables
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**/
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typedef struct {
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UPD_IIO_BIFURCATION_DATA_ENTRY *IIoBifurcationTable;
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UINT32 NumberOfEntries;
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} IIOBIFURCATION_CONFIG;
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/**
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VTD_CONFIG :
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VT direct IO Configuration Support
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VTdSupport - Enable/Disable VTd Support
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CoherencySupport - Enable/Disable Coherency Support
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ATS - Enable/Disable Address Translation Services
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FSP Will Disable VTd by default
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**/
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typedef struct {
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UINT8 VTdSupport;
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UINT8 CoherencySupport;
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UINT8 ATS;
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} VTD_CONFIG;
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/**
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UPD_PCIE_PORT_CONFIG
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PCIe port configuration
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PortIndex - Index of the port to be configured as defined by PCI_PORTS
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HidePort - Hide the selected port
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DeEmphasis - DeEmphasis of the selected PCIe port
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PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set
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DfxDnTxPreset - PCIe Downstream Tx Preset, valid values (0x00 - 0x09,
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0xFF is Auto, Auto sets 0x07)
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DfxRxPreset - PCIe Downstream Rx Preset, valid values (0x00 - 0x06, 0xFF is Auto)
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DfxUpTxPreset - PCIe Upstream Tx Preset, valid values (0x00 - 0x09, 0xFF is Auto)
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Sris - Enable/Disable SRIS (0x00 - Disable, 0x01 - Enable)
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PcieCommonClock - Configure port clocking. (0x00 - Distinct, 0x01 - Common)
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MaxPayload - PCIe Max Payload Size on the port
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NtbPpd - NTB port Configuration as defined in NTB_PPD
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NtbSplitBar - 0: Use one 64, 1: Use two 32-bit split bars
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NtbSBar01Prefetch - Configure Split BAR 0/1 as prefetchable
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NtbXlinkCtlOverride - NTB Cross-link as defined in NTB_XLINK
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NtbBarSizePBar4 - Set Prefetchable BAR 4 size for the primary NTB side in case
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Split Bar is Enabled
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NtbBarSizePBar5 - Set Prefetchable BAR 5 size for the primary NTB side in case
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Split Bar is Enabled
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FSP_WA: Till FSP fixes NtbBarSizeOverride, parameters below are MANDATORY!:
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These BAR size registers are write once registers and will be programmed with 0
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if not passed as FSP is
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hardcoding NtbBarSizeOverride to 0x01 for now.
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Split BAR sizes would need to be programmed mandatorily as well in case split bars
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are enabled.
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NtbBarSizePBar23 - Set Prefetchable BAR 23 size for the primary NTB side
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NtbBarSizePBar45 - Used to set bar 4 and 5 sizes in case Split Bar is Disabled
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NtbBarSizeSBar23 - Set Prefetchable BAR 23 size for the secondary NTB side
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NtbBarSizeSBar45 - Set Prefetchable BAR 45 size for the secondary NTB side in case
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Split Bar is disabled
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**/
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typedef struct {
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UINT32 PortIndex;
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UINT8 HidePort;
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UINT8 DeEmphasis;
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UINT8 PortLinkSpeed;
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UINT8 MaxPayload;
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UINT8 DfxDnTxPreset;
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UINT8 DfxRxPreset;
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UINT8 DfxUpTxPreset;
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UINT8 Sris;
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UINT8 PcieCommonClock;
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UINT8 NtbPpd;
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UINT8 NtbSplitBar;
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UINT8 NtbBarSizePBar23;
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UINT8 NtbBarSizePBar4;
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UINT8 NtbBarSizePBar5;
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UINT8 NtbBarSizePBar45;
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UINT8 NtbBarSizeSBar23;
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UINT8 NtbBarSizeSBar4;
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UINT8 NtbBarSizeSBar5;
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UINT8 NtbBarSizeSBar45;
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UINT8 NtbSBar01Prefetch;
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UINT8 NtbXlinkCtlOverride;
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} UPD_PCI_PORT_CONFIG;
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|
|
||||||
|
/**
|
||||||
|
PCIEPORT_CONFIG:
|
||||||
|
PciePortConfiguration - Pointer to an array of PCIe port configuration structures
|
||||||
|
as declared above
|
||||||
|
NumberOfEntries - Number of elements in the PciePortConfiguration Array
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
UPD_PCI_PORT_CONFIG *ConfigurationTable;
|
||||||
|
|
||||||
|
UINT16 NumberOfEntries;
|
||||||
|
} IIOPCIPORT_CONFIG;
|
||||||
|
|
||||||
|
/**
|
||||||
|
UPD_IIO_STACK_RESOURCE_CONFIG:
|
||||||
|
StackIndex - Index of the CPU IIO Stack to be configured as defined by IIO_STACKS
|
||||||
|
PciResourceIoBase
|
||||||
|
PciResourceIoLimit
|
||||||
|
PciResourceMem32Base
|
||||||
|
PciResourceMem32Limit
|
||||||
|
PciResourceMem64Base
|
||||||
|
PciResourceMem64Limit
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
UINT8 StackIndex;
|
||||||
|
UINT16 PciResourceIoBase;
|
||||||
|
UINT16 PciResourceIoLimit;
|
||||||
|
UINT32 PciResourceMem32Base;
|
||||||
|
UINT32 PciResourceMem32Limit;
|
||||||
|
UINT64 PciResourceMem64Base;
|
||||||
|
UINT64 PciResourceMem64Limit;
|
||||||
|
} UPD_IIO_STACK_RESOURCE_CONFIG;
|
||||||
|
|
||||||
|
/**
|
||||||
|
IIORESOURCE_CONFIG:
|
||||||
|
ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array
|
||||||
|
NumberOfEntries - Number of Entries in the Iio Stack Resource Configuration Array
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
UPD_IIO_STACK_RESOURCE_CONFIG *ResourceTable;
|
||||||
|
UINT16 NumberOfEntries;
|
||||||
|
} IIORESOURCE_CONFIG;
|
||||||
|
|
||||||
|
/**
|
||||||
|
UPD_PCH_PCIE_PORT:
|
||||||
|
PortIndex - PCH PCIe Port Index.
|
||||||
|
Valid Port Numbers are: 0 to 19.
|
||||||
|
Enable - Enable/Disable PCH PCIe port
|
||||||
|
PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
UINT8 PortIndex;
|
||||||
|
UINT8 ForceEnable;
|
||||||
|
UINT8 PortLinkSpeed;
|
||||||
|
} UPD_PCH_PCIE_PORT;
|
||||||
|
|
||||||
|
/**
|
||||||
|
PCHPCIPORT_CONFIG:
|
||||||
|
PciPortConfig - Pointer to an array of PCH PCI Ports to be configured
|
||||||
|
RootPortFunctionSwapping - Disable root port swapping based on device
|
||||||
|
connection status
|
||||||
|
PciePllSsc - Specifies the Pcie Pll Spread Spectrum Percentage
|
||||||
|
The value of this policy is in 1/10th percent units.
|
||||||
|
Valid spread range: 0-20. Auto: 0xFE (sets it to hardware default)
|
||||||
|
Completely Disable PCIe PLL SSC: 0xFF
|
||||||
|
A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
|
||||||
|
NumberOfEntries - Number of entries in the PCH PCI Port configuration
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
UPD_PCH_PCIE_PORT *PciPortConfig;
|
||||||
|
UINT8 RootPortFunctionSwapping;
|
||||||
|
UINT8 PciePllSsc;
|
||||||
|
UINT16 NumberOfEntries;
|
||||||
|
} PCHPCIPORT_CONFIG;
|
||||||
|
|
||||||
|
/** FSP-M Configuration
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
|
||||||
|
/** Offset 0x0040 - MRC Debug Print Level
|
||||||
|
Select the FSP MRC debug message print level. Options are a bitmask, so you can
|
||||||
|
combine options. BIT0:MIN DEBUG, BIT1:MAX DEBUG, BIT2:TRACE, BIT3:MEM TRAIN, BIT4:TEST,
|
||||||
|
BIT5:CPGC, BIT6:REG ACCESS
|
||||||
|
**/
|
||||||
|
UINT8 PcdFspMrcDebugPrintErrorLevel;
|
||||||
|
|
||||||
|
/** Offset 0x0041 - KTI Debug Print Level
|
||||||
|
Select the FSP KTI debug message print level. Options are a bitmask, so you can
|
||||||
|
combine options. BIT0:ERROR, BIT1:WARNING, BIT2:INFO0, BIT3:INFO1
|
||||||
|
**/
|
||||||
|
UINT8 PcdFspKtiDebugPrintErrorLevel;
|
||||||
|
|
||||||
|
/** Offset 0x0042 - HSUART Device
|
||||||
|
Select the PCI High Speed UART Device for Serial Port.
|
||||||
|
0:HSUART0, 1:HSUART1, 2:HSUART2
|
||||||
|
**/
|
||||||
|
UINT8 PcdHsuartDevice;
|
||||||
|
|
||||||
|
/** Offset 0x0043 - Customer Revision
|
||||||
|
The Customer can set this revision string for their own purpose.
|
||||||
|
**/
|
||||||
|
UINT8 PcdCustomerRevision[32];
|
||||||
|
|
||||||
|
/** Offset 0x0063 - GpioConfig
|
||||||
|
GpioConfig Struct. Defaults: GpioTable:NULL, NumberOfEntries:0x00
|
||||||
|
**/
|
||||||
|
GPIOTABLE_CONFIG GpioConfig;
|
||||||
|
|
||||||
|
/** Offset 0x006B - IioBifurcationConfig
|
||||||
|
IioBifurcationConfig Table Struct. Defaults: IioBifurcationTable:NULL,
|
||||||
|
NumberOfEntries:0x00
|
||||||
|
**/
|
||||||
|
IIOBIFURCATION_CONFIG IioBifurcationConfig;
|
||||||
|
|
||||||
|
/** Offset 0x0073
|
||||||
|
**/
|
||||||
|
UINT8 UnusedUpdSpace0[16];
|
||||||
|
|
||||||
|
/** Offset 0x0083 - VTdConfig
|
||||||
|
VTdConfig Struct. Defaults: All values are set to 0. VTd Disabled.
|
||||||
|
**/
|
||||||
|
VTD_CONFIG VTdConfig;
|
||||||
|
|
||||||
|
UINT8 reserved1[35];
|
||||||
|
|
||||||
|
/** Offset 0x00A9 - Board ID Number
|
||||||
|
Select the BoardId based on the target Platform. Default assumes an unknown board.
|
||||||
|
**/
|
||||||
|
UINT8 BoardId;
|
||||||
|
|
||||||
|
UINT8 reserved2[24];
|
||||||
|
|
||||||
|
/** Offset 0x00C2 **/
|
||||||
|
VOID *SetupStructPtr;
|
||||||
|
|
||||||
|
UINT8 reserved3[20];
|
||||||
|
|
||||||
|
/** Offset 0x00DA - IioPciConfig
|
||||||
|
IIO Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero.
|
||||||
|
**/
|
||||||
|
IIOPCIPORT_CONFIG IioPciConfig;
|
||||||
|
|
||||||
|
/** Offset 0x00E0 - PchPciConfig
|
||||||
|
PCH Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero.
|
||||||
|
**/
|
||||||
|
PCHPCIPORT_CONFIG PchPciConfig;
|
||||||
|
|
||||||
|
/** Offset 0x00E8 - IioResourceConfig
|
||||||
|
IIO Resource Struct. Defaults: All pointers are NULL. All values are set to zero.
|
||||||
|
**/
|
||||||
|
IIORESOURCE_CONFIG IioResourceConfig;
|
||||||
|
|
||||||
|
UINT8 reserved4[3];
|
||||||
|
|
||||||
|
/** Offset 0x00F1 - DCI Enable
|
||||||
|
Enable / Disable DCI
|
||||||
|
$EN_DIS
|
||||||
|
**/
|
||||||
|
UINT8 PchDciEn;
|
||||||
|
|
||||||
|
/** Offset 0x00F2 - IO Margining Tool (IOMT) Enable
|
||||||
|
Enable / Disable Io Margining Tool
|
||||||
|
$EN_DIS
|
||||||
|
**/
|
||||||
|
UINT8 IomtEnable;
|
||||||
|
|
||||||
|
/** Offset 0x00F3 - Hyper Threading (HT) disable
|
||||||
|
Disable Hyper threading. Disable: 0x01 | Enable: 0x00 | Default - HT enabled
|
||||||
|
$EN_DIS
|
||||||
|
**/
|
||||||
|
UINT8 HyperThreadingDisable;
|
||||||
|
|
||||||
|
/** Offset 0x00F4
|
||||||
|
**/
|
||||||
|
UINT8 UnusedUpdSpace1[236];
|
||||||
|
|
||||||
|
/** Offset 0x01E0
|
||||||
|
**/
|
||||||
|
UINT8 ReservedMemoryInitUpd[16];
|
||||||
|
} FSP_M_CONFIG;
|
||||||
|
|
||||||
|
/** Fsp M UPD Configuration
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
|
||||||
|
/** Offset 0x0000
|
||||||
|
**/
|
||||||
|
FSP_UPD_HEADER FspUpdHeader;
|
||||||
|
|
||||||
|
/** Offset 0x0020
|
||||||
|
**/
|
||||||
|
FSPM_ARCH_UPD FspmArchUpd;
|
||||||
|
|
||||||
|
/** Offset 0x0040
|
||||||
|
**/
|
||||||
|
FSP_M_CONFIG FspmConfig;
|
||||||
|
|
||||||
|
/** Offset 0x01F0 - FspmVersion
|
||||||
|
FSP-M UPD Version Number
|
||||||
|
**/
|
||||||
|
UINT16 FspmUpdVersion;
|
||||||
|
|
||||||
|
/** Offset 0x01F2
|
||||||
|
**/
|
||||||
|
UINT8 UnusedUpdSpace2[12];
|
||||||
|
|
||||||
|
/** Offset 0x01FE
|
||||||
|
**/
|
||||||
|
UINT16 UpdTerminator;
|
||||||
|
} FSPM_UPD;
|
||||||
|
|
||||||
|
#pragma pack()
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,198 @@
|
||||||
|
/** @file
|
||||||
|
|
||||||
|
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer in the documentation and/or
|
||||||
|
other materials provided with the distribution.
|
||||||
|
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||||
|
be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||||
|
THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
This file is automatically generated. Please do NOT modify !!!
|
||||||
|
|
||||||
|
**/
|
||||||
|
|
||||||
|
#ifndef __FSPSUPD_H__
|
||||||
|
#define __FSPSUPD_H__
|
||||||
|
|
||||||
|
#include <FspUpd.h>
|
||||||
|
|
||||||
|
#pragma pack(1)
|
||||||
|
|
||||||
|
|
||||||
|
/** FSP-S Configuration
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
|
||||||
|
/** Offset 0x0020 - PCIe Controller 0 Bifurcation
|
||||||
|
Configure PCI Express controller 0 bifurcation.
|
||||||
|
0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8
|
||||||
|
**/
|
||||||
|
UINT8 PcdBifurcationPcie0;
|
||||||
|
|
||||||
|
/** Offset 0x0021 - PCIe Controller 1 Bifurcation
|
||||||
|
Configure PCI Express controller 1 bifurcation.
|
||||||
|
0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8
|
||||||
|
**/
|
||||||
|
UINT8 PcdBifurcationPcie1;
|
||||||
|
|
||||||
|
/** Offset 0x0022 - Active Core Count
|
||||||
|
Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores)
|
||||||
|
0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13,
|
||||||
|
14:14, 15:15
|
||||||
|
**/
|
||||||
|
UINT8 PcdActiveCoreCount;
|
||||||
|
|
||||||
|
/** Offset 0x0023
|
||||||
|
**/
|
||||||
|
UINT32 PcdCpuMicrocodePatchBase;
|
||||||
|
|
||||||
|
/** Offset 0x0027
|
||||||
|
**/
|
||||||
|
UINT32 PcdCpuMicrocodePatchSize;
|
||||||
|
|
||||||
|
/** Offset 0x002B - PCIe Controller 0
|
||||||
|
Enable / Disable PCI Express controller 0
|
||||||
|
$EN_DIS
|
||||||
|
**/
|
||||||
|
UINT8 PcdEnablePcie0;
|
||||||
|
|
||||||
|
/** Offset 0x002C - PCIe Controller 1
|
||||||
|
Enable / Disable PCI Express controller 1
|
||||||
|
$EN_DIS
|
||||||
|
**/
|
||||||
|
UINT8 PcdEnablePcie1;
|
||||||
|
|
||||||
|
/** Offset 0x002D - Embedded Multi-Media Controller (eMMC)
|
||||||
|
Enable / Disable Embedded Multi-Media controller
|
||||||
|
$EN_DIS
|
||||||
|
**/
|
||||||
|
UINT8 PcdEnableEmmc;
|
||||||
|
|
||||||
|
/** Offset 0x002E - LAN Controllers
|
||||||
|
Enable / Disable LAN controllers, refer to FSP Integration Guide for details.
|
||||||
|
0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
|
||||||
|
**/
|
||||||
|
UINT8 PcdEnableGbE;
|
||||||
|
|
||||||
|
/** Offset 0x002F
|
||||||
|
**/
|
||||||
|
UINT32 PcdFiaMuxConfigRequestPtr;
|
||||||
|
|
||||||
|
/** Offset 0x0033
|
||||||
|
**/
|
||||||
|
UINT8 UnusedUpdSpace0[4];
|
||||||
|
|
||||||
|
/** Offset 0x0037 - PCIe Root Port 0 DeEmphasis
|
||||||
|
Desired DeEmphasis level for PCIE root port
|
||||||
|
0:6dB, 1:3.5dB
|
||||||
|
**/
|
||||||
|
UINT8 PcdPcieRootPort0DeEmphasis;
|
||||||
|
|
||||||
|
/** Offset 0x0038 - PCIe Root Port 1 DeEmphasis
|
||||||
|
Desired DeEmphasis level for PCIE root port
|
||||||
|
0:6dB, 1:3.5dB
|
||||||
|
**/
|
||||||
|
UINT8 PcdPcieRootPort1DeEmphasis;
|
||||||
|
|
||||||
|
/** Offset 0x0039 - PCIe Root Port 2 DeEmphasis
|
||||||
|
Desired DeEmphasis level for PCIE root port
|
||||||
|
0:6dB, 1:3.5dB
|
||||||
|
**/
|
||||||
|
UINT8 PcdPcieRootPort2DeEmphasis;
|
||||||
|
|
||||||
|
/** Offset 0x003A - PCIe Root Port 3 DeEmphasis
|
||||||
|
Desired DeEmphasis level for PCIE root port
|
||||||
|
0:6dB, 1:3.5dB
|
||||||
|
**/
|
||||||
|
UINT8 PcdPcieRootPort3DeEmphasis;
|
||||||
|
|
||||||
|
/** Offset 0x003B - PCIe Root Port 4 DeEmphasis
|
||||||
|
Desired DeEmphasis level for PCIE root port
|
||||||
|
0:6dB, 1:3.5dB
|
||||||
|
**/
|
||||||
|
UINT8 PcdPcieRootPort4DeEmphasis;
|
||||||
|
|
||||||
|
/** Offset 0x003C - PCIe Root Port 5 DeEmphasis
|
||||||
|
Desired DeEmphasis level for PCIE root port
|
||||||
|
0:6dB, 1:3.5dB
|
||||||
|
**/
|
||||||
|
UINT8 PcdPcieRootPort5DeEmphasis;
|
||||||
|
|
||||||
|
/** Offset 0x003D - PCIe Root Port 6 DeEmphasis
|
||||||
|
Desired DeEmphasis level for PCIE root port
|
||||||
|
0:6dB, 1:3.5dB
|
||||||
|
**/
|
||||||
|
UINT8 PcdPcieRootPort6DeEmphasis;
|
||||||
|
|
||||||
|
/** Offset 0x003E - PCIe Root Port 7 DeEmphasis
|
||||||
|
Desired DeEmphasis level for PCIE root port
|
||||||
|
0:6dB, 1:3.5dB
|
||||||
|
**/
|
||||||
|
UINT8 PcdPcieRootPort7DeEmphasis;
|
||||||
|
|
||||||
|
/** Offset 0x003F
|
||||||
|
**/
|
||||||
|
UINT8 UnusedUpdSpace1;
|
||||||
|
|
||||||
|
/** Offset 0x0040
|
||||||
|
**/
|
||||||
|
UINT32 PcdEMMCDLLConfigPtr;
|
||||||
|
|
||||||
|
/** Offset 0x0044 - Disable Monitor MWAIT
|
||||||
|
Enable / Disable the Monitor-MWAIT Instruction
|
||||||
|
$EN_DIS
|
||||||
|
**/
|
||||||
|
UINT8 PcdDisableMonitorFSM;
|
||||||
|
|
||||||
|
/** Offset 0x0045
|
||||||
|
**/
|
||||||
|
UINT8 UnusedUpdSpace2[155];
|
||||||
|
|
||||||
|
/** Offset 0x00E0
|
||||||
|
**/
|
||||||
|
UINT8 ReservedSiliconInitUpd[16];
|
||||||
|
} FSPS_CONFIG;
|
||||||
|
|
||||||
|
/** Fsp S UPD Configuration
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
|
||||||
|
/** Offset 0x0000
|
||||||
|
**/
|
||||||
|
FSP_UPD_HEADER FspUpdHeader;
|
||||||
|
|
||||||
|
/** Offset 0x0020
|
||||||
|
**/
|
||||||
|
FSPS_CONFIG FspsConfig;
|
||||||
|
|
||||||
|
/** Offset 0x00F0
|
||||||
|
**/
|
||||||
|
UINT8 UnusedUpdSpace3[14];
|
||||||
|
|
||||||
|
/** Offset 0x00FE
|
||||||
|
**/
|
||||||
|
UINT16 UpdTerminator;
|
||||||
|
} FSPS_UPD;
|
||||||
|
|
||||||
|
#pragma pack()
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,108 @@
|
||||||
|
/** @file
|
||||||
|
|
||||||
|
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer in the documentation and/or
|
||||||
|
other materials provided with the distribution.
|
||||||
|
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||||
|
be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||||
|
THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
This file is automatically generated. Please do NOT modify !!!
|
||||||
|
|
||||||
|
**/
|
||||||
|
|
||||||
|
#ifndef __FSPTUPD_H__
|
||||||
|
#define __FSPTUPD_H__
|
||||||
|
|
||||||
|
#include <FspUpd.h>
|
||||||
|
|
||||||
|
#pragma pack(1)
|
||||||
|
|
||||||
|
/** FSP-T Core UPD
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
|
||||||
|
/** Offset 0x0020
|
||||||
|
**/
|
||||||
|
UINT32 MicrocodeRegionBase;
|
||||||
|
|
||||||
|
/** Offset 0x0024
|
||||||
|
**/
|
||||||
|
UINT32 MicrocodeRegionLength;
|
||||||
|
|
||||||
|
/** Offset 0x0028
|
||||||
|
**/
|
||||||
|
UINT32 CodeRegionBase;
|
||||||
|
|
||||||
|
/** Offset 0x002C
|
||||||
|
**/
|
||||||
|
UINT32 CodeRegionLength;
|
||||||
|
|
||||||
|
/** Offset 0x0030
|
||||||
|
**/
|
||||||
|
UINT8 Reserved1[16];
|
||||||
|
} FSPT_CORE_UPD;
|
||||||
|
|
||||||
|
/** FSP-T Configuration
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
|
||||||
|
/** Offset 0x0040 - Disable Port80 output in FSP-T
|
||||||
|
Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80
|
||||||
|
Output, refer to FSP Integration Guide for details
|
||||||
|
0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
|
||||||
|
**/
|
||||||
|
UINT8 PcdFsptPort80RouteDisable;
|
||||||
|
|
||||||
|
/** Offset 0x0041
|
||||||
|
**/
|
||||||
|
UINT8 ReservedTempRamInitUpd[31];
|
||||||
|
} FSPT_CONFIG;
|
||||||
|
|
||||||
|
/** Fsp T UPD Configuration
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
|
||||||
|
/** Offset 0x0000
|
||||||
|
**/
|
||||||
|
FSP_UPD_HEADER FspUpdHeader;
|
||||||
|
|
||||||
|
/** Offset 0x0020
|
||||||
|
**/
|
||||||
|
FSPT_CORE_UPD FsptCoreUpd;
|
||||||
|
|
||||||
|
/** Offset 0x0040
|
||||||
|
**/
|
||||||
|
FSPT_CONFIG FsptConfig;
|
||||||
|
|
||||||
|
/** Offset 0x0060
|
||||||
|
**/
|
||||||
|
UINT8 UnusedUpdSpace0[30];
|
||||||
|
|
||||||
|
/** Offset 0x007E
|
||||||
|
**/
|
||||||
|
UINT16 UpdTerminator;
|
||||||
|
} FSPT_UPD;
|
||||||
|
|
||||||
|
#pragma pack()
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,244 @@
|
||||||
|
/**
|
||||||
|
Copyright (c) 2019-2020, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer in the documentation and/or
|
||||||
|
other materials provided with the distribution.
|
||||||
|
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||||
|
be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||||
|
THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
**/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef _HOB_IIOUDS_H_
|
||||||
|
#define _HOB_IIOUDS_H_
|
||||||
|
|
||||||
|
#include <fsp/util.h>
|
||||||
|
|
||||||
|
#define FSP_HOB_IIO_UNIVERSAL_DATA_GUID { \
|
||||||
|
0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \
|
||||||
|
0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define NUMBER_PORTS_PER_SOCKET 21
|
||||||
|
#define MAX_SOCKET CONFIG_MAX_SOCKET
|
||||||
|
#define MAX_IIO MAX_SOCKET
|
||||||
|
#define MAX_IIO_STACK 6
|
||||||
|
#define MAX_KTI_PORTS 3
|
||||||
|
#define MAX_IMC 2
|
||||||
|
#define MAX_CH 6
|
||||||
|
#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC)
|
||||||
|
#define SAD_RULES 24
|
||||||
|
#define TDP_MAX_LEVEL 5
|
||||||
|
|
||||||
|
#pragma pack(1)
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------------------------//
|
||||||
|
// Structure definitions for Universal Data Store (UDS)
|
||||||
|
//--------------------------------------------------------------------------------------//
|
||||||
|
typedef struct uint64_t_struct {
|
||||||
|
uint32_t lo;
|
||||||
|
uint32_t hi;
|
||||||
|
} UINT64_STRUCT;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uint8_t Device;
|
||||||
|
uint8_t Function;
|
||||||
|
} IIO_PORT_INFO;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
// TRUE, if the link is valid (i.e reached normal operation)
|
||||||
|
uint8_t Valid;
|
||||||
|
uint8_t PeerSocId; // Socket ID
|
||||||
|
uint8_t PeerSocType; // Socket Type (0 - CPU; 1 - IIO)
|
||||||
|
uint8_t PeerPort; // Port of the peer socket
|
||||||
|
} QPI_PEER_DATA;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uint8_t Valid;
|
||||||
|
uint8_t SocketFirstBus;
|
||||||
|
uint8_t SocketLastBus;
|
||||||
|
uint8_t segmentSocket;
|
||||||
|
uint8_t PcieSegment;
|
||||||
|
UINT64_STRUCT SegMmcfgBase;
|
||||||
|
uint8_t stackPresentBitmap;
|
||||||
|
uint8_t StackBus[MAX_IIO_STACK];
|
||||||
|
uint8_t M2PciePresentBitmap;
|
||||||
|
uint8_t TotM3Kti;
|
||||||
|
uint8_t TotCha;
|
||||||
|
uint32_t ChaList;
|
||||||
|
uint32_t SocId;
|
||||||
|
QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info
|
||||||
|
} QPI_CPU_DATA;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uint8_t Valid;
|
||||||
|
uint8_t SocId;
|
||||||
|
QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
|
||||||
|
} QPI_IIO_DATA;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET];
|
||||||
|
} IIO_DMI_PCIE_INFO;
|
||||||
|
|
||||||
|
typedef struct _STACK_RES {
|
||||||
|
uint8_t Personality;
|
||||||
|
uint8_t BusBase;
|
||||||
|
uint8_t BusLimit;
|
||||||
|
uint16_t PciResourceIoBase;
|
||||||
|
uint16_t PciResourceIoLimit;
|
||||||
|
uint32_t IoApicBase;
|
||||||
|
uint32_t IoApicLimit;
|
||||||
|
uint32_t PciResourceMem32Base;
|
||||||
|
uint32_t PciResourceMem32Limit;
|
||||||
|
uint64_t PciResourceMem64Base;
|
||||||
|
uint64_t PciResourceMem64Limit;
|
||||||
|
uint32_t VtdBarAddress;
|
||||||
|
} STACK_RES;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uint8_t Valid;
|
||||||
|
int8_t SocketID; // Socket ID of the IIO (0..3)
|
||||||
|
uint8_t BusBase;
|
||||||
|
uint8_t BusLimit;
|
||||||
|
uint16_t PciResourceIoBase;
|
||||||
|
uint16_t PciResourceIoLimit;
|
||||||
|
uint32_t IoApicBase;
|
||||||
|
uint32_t IoApicLimit;
|
||||||
|
uint32_t PciResourceMem32Base;
|
||||||
|
uint32_t PciResourceMem32Limit;
|
||||||
|
uint64_t PciResourceMem64Base;
|
||||||
|
uint64_t PciResourceMem64Limit;
|
||||||
|
STACK_RES StackRes[MAX_IIO_STACK];
|
||||||
|
uint32_t RcBaseAddress;
|
||||||
|
IIO_DMI_PCIE_INFO PcieInfo;
|
||||||
|
uint8_t DmaDeviceCount;
|
||||||
|
} IIO_RESOURCE_INSTANCE;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uint16_t PlatGlobalIoBase; // Global IO Base
|
||||||
|
uint16_t PlatGlobalIoLimit; // Global IO Limit
|
||||||
|
uint32_t PlatGlobalMmiolBase; // Global Mmiol base
|
||||||
|
uint32_t PlatGlobalMmiolLimit; // Global Mmiol limit
|
||||||
|
uint64_t PlatGlobalMmiohBase; // Global Mmioh Base [43:0]
|
||||||
|
uint64_t PlatGlobalMmiohLimit; // Global Mmioh Limit [43:0]
|
||||||
|
QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
|
||||||
|
QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
|
||||||
|
uint32_t MemTsegSize;
|
||||||
|
uint32_t MemIedSize;
|
||||||
|
uint64_t PciExpressBase;
|
||||||
|
uint32_t PciExpressSize;
|
||||||
|
uint32_t MemTolm;
|
||||||
|
IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET];
|
||||||
|
uint8_t numofIIO;
|
||||||
|
uint8_t MaxBusNumber;
|
||||||
|
// This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
|
||||||
|
uint32_t packageBspApicID[MAX_SOCKET];
|
||||||
|
uint8_t EVMode;
|
||||||
|
uint8_t Pci64BitResourceAllocation;
|
||||||
|
uint8_t SkuPersonality[MAX_SOCKET];
|
||||||
|
uint8_t VMDStackEnable[MAX_IIO][MAX_IIO_STACK];
|
||||||
|
uint16_t IoGranularity;
|
||||||
|
uint32_t MmiolGranularity;
|
||||||
|
UINT64_STRUCT MmiohGranularity;
|
||||||
|
uint8_t RemoteRequestThreshold;
|
||||||
|
// bitmap of Softsku sockets with CPUs present detected
|
||||||
|
uint64_t softskuSocketPresentBitMap;
|
||||||
|
BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w
|
||||||
|
} PLATFORM_DATA;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uint32_t FILLER_BUG;
|
||||||
|
// Current programmed CSI (or UPI) Link speed (Slow/Full speed mode)
|
||||||
|
uint8_t CurrentCsiLinkSpeed;
|
||||||
|
// Current requested CSI (or UPI) Link frequency (in GT)
|
||||||
|
uint8_t CurrentCsiLinkFrequency;
|
||||||
|
// output kti link enabled status for PM
|
||||||
|
uint32_t OutKtiPerLinkL1En[MAX_SOCKET];
|
||||||
|
uint8_t IsocEnable;
|
||||||
|
// Size of the memory range requested by ME FW, in MB
|
||||||
|
uint32_t meRequestedSize;
|
||||||
|
uint8_t DmiVc1;
|
||||||
|
uint8_t DmiVcm;
|
||||||
|
uint32_t CpuPCPSInfo;
|
||||||
|
uint8_t MinimumCpuStepping;
|
||||||
|
uint8_t LtsxEnable;
|
||||||
|
uint8_t MctpEn;
|
||||||
|
uint8_t cpuType;
|
||||||
|
uint8_t cpuSubType;
|
||||||
|
uint8_t SystemRasType;
|
||||||
|
// 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
|
||||||
|
uint8_t numCpus;
|
||||||
|
// Fused Core Mask in the package
|
||||||
|
uint32_t FusedCores[MAX_SOCKET];
|
||||||
|
// Current activated core Mask in the package
|
||||||
|
uint32_t ActiveCores[MAX_SOCKET];
|
||||||
|
// Package Max Non-turbo Ratio (per socket).
|
||||||
|
uint8_t MaxCoreToBusRatio[MAX_SOCKET];
|
||||||
|
// Package Maximum Efficiency Ratio (per socket).
|
||||||
|
uint8_t MinCoreToBusRatio[MAX_SOCKET];
|
||||||
|
uint8_t CurrentCoreToBusRatio; // Current system Core to Bus Ratio
|
||||||
|
// ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8]
|
||||||
|
uint32_t IntelSpeedSelectCapable;
|
||||||
|
uint32_t IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO
|
||||||
|
// get B2P CONFIG_TDP_GET_TDP_INFO
|
||||||
|
uint32_t IssConfigTdpTdpInfo[TDP_MAX_LEVEL];
|
||||||
|
// get B2P CONFIG_TDP_GET_POWER_INFO
|
||||||
|
uint32_t IssConfigTdpPowerInfo[TDP_MAX_LEVEL];
|
||||||
|
// get B2P CONFIG_TDP_GET_CORE_COUNT
|
||||||
|
uint8_t IssConfigTdpCoreCount[TDP_MAX_LEVEL];
|
||||||
|
// bitmap of sockets with CPUs present detected by QPI RC
|
||||||
|
uint32_t socketPresentBitMap;
|
||||||
|
// bitmap of NID w/ fpga present detected by QPI RC
|
||||||
|
uint32_t FpgaPresentBitMap;
|
||||||
|
uint16_t tolmLimit;
|
||||||
|
uint32_t tohmLimit;
|
||||||
|
uint32_t mmCfgBase;
|
||||||
|
uint32_t RcVersion;
|
||||||
|
uint8_t DdrXoverMode; // DDR 2.2 Mode
|
||||||
|
uint8_t bootMode;
|
||||||
|
uint8_t OutClusterOnDieEn; // Whether RC enabled COD support
|
||||||
|
uint8_t OutSncEn;
|
||||||
|
uint8_t OutNumOfCluster;
|
||||||
|
uint8_t imcEnabled[MAX_SOCKET][MAX_IMC];
|
||||||
|
uint8_t numChPerMC;
|
||||||
|
uint8_t maxCh;
|
||||||
|
uint8_t maxIMC;
|
||||||
|
uint16_t LlcSizeReg;
|
||||||
|
uint8_t chEnabled[MAX_SOCKET][MAX_CH];
|
||||||
|
uint8_t mcId[MAX_SOCKET][MAX_CH];
|
||||||
|
uint8_t memNode[MC_MAX_NODE];
|
||||||
|
uint8_t IoDcMode;
|
||||||
|
uint8_t CpuAccSupport;
|
||||||
|
uint8_t SmbusErrorRecovery;
|
||||||
|
uint8_t AepDimmPresent;
|
||||||
|
} SYSTEM_STATUS;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
PLATFORM_DATA PlatformData;
|
||||||
|
SYSTEM_STATUS SystemStatus;
|
||||||
|
uint32_t OemValue;
|
||||||
|
} IIO_UDS;
|
||||||
|
#pragma pack()
|
||||||
|
|
||||||
|
void soc_display_iio_universal_data_hob(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,119 @@
|
||||||
|
/**
|
||||||
|
Copyright (c) 2019-2020, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer in the documentation and/or
|
||||||
|
other materials provided with the distribution.
|
||||||
|
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||||
|
be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||||
|
THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
**/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef _MEMORY_MAP_GUID_H_
|
||||||
|
#define _MEMORY_MAP_GUID_H_
|
||||||
|
|
||||||
|
#define FSP_SYSTEM_MEMORYMAP_HOB_GUID { \
|
||||||
|
0x15, 0x00, 0x87, 0xf8, 0x94, 0x69, 0x98, 0x4b, 0x95, 0xa2, \
|
||||||
|
0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define MEMTYPE_1LM_MASK (1 << 0)
|
||||||
|
#define MEMTYPE_2LM_MASK (1 << 1)
|
||||||
|
#define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK)
|
||||||
|
|
||||||
|
#define MAX_IMC_PER_SOCKET 2
|
||||||
|
#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8
|
||||||
|
#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \
|
||||||
|
MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \
|
||||||
|
)
|
||||||
|
|
||||||
|
/* ACPI SRAT Memory Flags */
|
||||||
|
#define SRAT_ACPI_MEMORY_ENABLED (1 << 0)
|
||||||
|
#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1)
|
||||||
|
#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2)
|
||||||
|
|
||||||
|
#define MEM_TYPE_RESERVED (1 << 8)
|
||||||
|
#define MEM_ADDR_64MB_SHIFT_BITS 26
|
||||||
|
|
||||||
|
//
|
||||||
|
// System Memory Map HOB information
|
||||||
|
//
|
||||||
|
|
||||||
|
#pragma pack(1)
|
||||||
|
|
||||||
|
struct SystemMemoryMapElement {
|
||||||
|
UINT8 NodeId; // Node ID of the HA Owning the memory
|
||||||
|
UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
|
||||||
|
UINT8 ImcInterBitmap; // IMC interleave bitmap for this DRAM rule - ONLY IN NUMA
|
||||||
|
UINT32 BaseAddress; // Base Address of the element in 64MB chunks
|
||||||
|
UINT32 ElementSize; // Size of this memory element in 64MB chunks
|
||||||
|
// Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM
|
||||||
|
// Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
|
||||||
|
UINT16 Type;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct SystemMemoryMapHob {
|
||||||
|
UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem.
|
||||||
|
UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem.
|
||||||
|
UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem.
|
||||||
|
UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem.
|
||||||
|
UINT32 asilLoMemBase; // Mem base in 64MB units for below 4GB mem.
|
||||||
|
UINT32 asilHiMemBase; // Mem base in 64MB units for above 4GB mem.
|
||||||
|
UINT32 asilLoMemSize; // Mem size in 64MB units for below 4GB mem.
|
||||||
|
UINT32 asilHiMemSize; // Mem size in 64MB units for above 4GB mem.
|
||||||
|
|
||||||
|
UINT32 memSize; // Total physical memory size
|
||||||
|
UINT16 memFreq; // Mem Frequency
|
||||||
|
UINT8 memMode; // 0 - Independent, 1 - Lockstep
|
||||||
|
UINT8 volMemMode; // 0 - 1LM, 1 - 2LM
|
||||||
|
UINT8 DimmType;
|
||||||
|
UINT16 DramType;
|
||||||
|
UINT8 DdrVoltage;
|
||||||
|
// If at least one Aep Dimm Present (used by Nfit), then this should get set
|
||||||
|
UINT8 AepDimmPresent;
|
||||||
|
UINT8 SADNum;
|
||||||
|
UINT8 XMPProfilesSup;
|
||||||
|
UINT8 cpuType;
|
||||||
|
UINT8 cpuStepping;
|
||||||
|
UINT8 SystemRasType;
|
||||||
|
UINT8 RasModesEnabled; // RAS modes that are enabled
|
||||||
|
UINT8 ExRasModesEnabled; // Extended RAS modes that are enabled
|
||||||
|
//RAS modes that are supported by current memory population.
|
||||||
|
UINT8 RasModesSupported;
|
||||||
|
// 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
|
||||||
|
UINT8 sncEnabled;
|
||||||
|
UINT8 NumOfCluster;
|
||||||
|
UINT8 NumChPerMC;
|
||||||
|
UINT8 numberEntries; // Number of Memory Map Elements
|
||||||
|
UINT8 maxIMC;
|
||||||
|
UINT8 maxCh;
|
||||||
|
struct SystemMemoryMapElement Element[MAX_SOCKET * SAD_RULES];
|
||||||
|
UINT8 reserved1[982];
|
||||||
|
UINT8 reserved2[4901*MAX_SOCKET];
|
||||||
|
UINT8 reserved3[707];
|
||||||
|
};
|
||||||
|
|
||||||
|
#pragma pack()
|
||||||
|
|
||||||
|
void soc_display_memmap_hob(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue