GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/ironlake: Add Generic Non-Core register definitions 

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-07-22 18:37:32 +02:00 committed by Patrick Georgi
parent c642a0d894
commit 9addda3c41
3 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/ironlake/early_init.c
View File

@ -43,7 +43,7 @@ static void early_cpu_init(void)
/* bit 0 = disable multicore,
bit 1 = disable quadcore,
bit 8 = disable hyperthreading. */
pci_update_config32(QPI_NON_CORE, 0x80, 0xfffffefc, 0x10000);
pci_update_config32(QPI_NON_CORE, DESIRED_CORES, 0xfffffefc, 0x10000);
u8 reg8;
struct cpuid_result result;

4
src/northbridge/intel/ironlake/ironlake.h
View File

@ -52,6 +52,10 @@
*/
#define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0)
#define MAX_RTIDS 0x60
#define DESIRED_CORES 0x80
#define MIRROR_PORT_CTL 0xd0
/*
* SAD - System Address Decoder
*/

6
src/northbridge/intel/ironlake/raminit.c
View File

@ -3955,8 +3955,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!!
pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555);
pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!!
pci_read_config32(QPI_NON_CORE, 0xd0); // !!!!
pci_write_config32(QPI_NON_CORE, 0xd0, 0x180);
pci_read_config32(QPI_NON_CORE, MIRROR_PORT_CTL); // !!!!
pci_write_config32(QPI_NON_CORE, MIRROR_PORT_CTL, 0x180);
gav(MCHBAR32(0x1af0)); // !!!!
gav(MCHBAR32(0x1af0)); // !!!!
MCHBAR32(0x1af0) = 0x1f020003;
@ -4225,7 +4225,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8);
MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!!
pci_write_config32(QPI_NON_CORE, 0x60, 0x20220);
pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220);
MCHBAR16(0x2c20); // !!!!
MCHBAR16(0x2c10); // !!!!
MCHBAR16(0x2c00); // !!!!