superio/nuvoton/npcd378: Add ACPI code for S3 resume
Configure SuperIO on shutdown to keep devices enabled, set green LED to fading on sleep and normal on wake. Add SSDT to write LDN4 IOBASE addresses stored in devicetree.cb. Tested on HP8200: * Wakes from power button or USB keyboard. * LED is fading Change-Id: I2035249a39616aa2d87bd93f9e49c70d231546cc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Patrick Rudolph
Patrick Georgi
parent
9990943782
commit
9ae150a591
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@ -78,14 +78,6 @@ Device(SUPERIO_DEV) {
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PNP_IRQ1, 8, /* Second IRQ */
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}
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Method (_CRS)
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{
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/* Announce the used I/O ports to the OS */
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Return (ResourceTemplate () {
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IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
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})
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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@ -165,4 +157,180 @@ Device(SUPERIO_DEV) {
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#include <superio/acpi/pnp_generic.asl>
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#endif
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// generated by SSDT
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External(SWB, IntObj)
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External(SWL, IntObj)
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OperationRegion (SWCR, SystemIO, SWB, SWL)
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Field (SWCR, ByteAcc, NoLock, Preserve)
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{
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LEDC, 8,
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SWCC, 8
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}
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// generated by SSDT
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External(RNB, IntObj)
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External(RNL, IntObj)
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OperationRegion (RNTR, SystemIO, RNB, RNL)
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Field (RNTR, ByteAcc, NoLock, Preserve)
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{
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GPES, 8,
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GPEE, 8,
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Offset (0x08),
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GPS0, 8,
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GPS1, 8,
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GPS2, 8,
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GPS3, 8,
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GPE0, 8,
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GPE1, 8,
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GPE2, 8,
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GPE3, 8
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}
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Name (MSFG, One)
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Name (KBFG, One)
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Name (PMFG, Zero) // Wake event backup
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Method (_CRS, 0, Serialized)
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{
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Name (CRS, ResourceTemplate ()
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{
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FixedIO (SUPERIO_PNP_BASE, 0x02)
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// filled below
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FixedIO (0, 0, CRS1)
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FixedIO (0, 0, CRS2)
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})
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CreateWordField (CRS, CRS1._BAS, TMP1)
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Store(SWB, TMP1)
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CreateByteField (CRS, CRS1._LEN, TMP2)
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Store(SWL, TMP2)
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CreateWordField (CRS, CRS2._BAS, TMP3)
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Store(RNB, TMP3)
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CreateByteField (CRS, CRS2._LEN, TMP4)
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Store(RNL, TMP4)
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/* Announce the used I/O ports to the OS */
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Return (CRS)
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}
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#ifdef SUPERIO_SHOW_KBC
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#if defined(SUPERIO_KBC_LDN)
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#define _PS2_KB SUPERIO_ID(KBD, SUPERIO_KBC_LDN)
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#else
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#define _PS2_KB PS2K
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#endif
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Scope (_PS2_KB)
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{
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Method (_PSW, 1, NotSerialized)
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{
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KBFG = Arg0
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}
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Method (_PRW, 0, NotSerialized)
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{
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Return (Package (0x02) {0x08, 0x03})
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}
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}
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#if defined(SUPERIO_KBC_PS2M)
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#define _PS2_M SUPERIO_ID(PS2, SUPERIO_KBC_PS2M)
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#elif defined(SUPERIO_KBC_PS2LDN)
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#define _PS2_M SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN)
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#else
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#define _PS2_M PS2M
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#endif
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Scope (_PS2_M)
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{
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Method (_PSW, 1, NotSerialized)
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{
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MSFG = Arg0
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}
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Method (_PRW, 0, NotSerialized)
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{
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Return (Package (0x02) {0x08, 0x03})
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}
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}
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Method (SIOH, 0, NotSerialized)
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{
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If ((PMFG & 0xE8))
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{
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Notify (_PS2_KB, 0x02)
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}
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If ((PMFG & 0x10))
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{
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Notify (_PS2_M, 0x02)
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}
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}
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#else
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Method (SIOH, 0, NotSerialized)
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{
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}
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#endif
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/* SuperIO sleep method */
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Method (SIOS, 1, NotSerialized)
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{
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If ((0x05 != Arg0))
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{
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/* Set PS/2 powerstate in S3 */
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If (KBFG)
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{
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GPE2 |= 0xE8
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}
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Else
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{
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GPE2 &= 0x17
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}
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If (MSFG)
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{
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GPE2 |= 0x10
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}
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Else
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{
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GPE2 &= 0xEF
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}
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/* Enable wake on GPE */
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GPEE = One
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If ((0x03 == Arg0))
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{
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/* green LED fading */
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Local1 = LEDC
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Local1 &= 0xE0
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LEDC = (Local1 | 0x1C)
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Local1 = SWCC
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Local1 &= 0xBF
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SWCC = (Local1 | 0x40)
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}
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}
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GPE0 = 0x10
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GPE1 = 0x20
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}
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/* SuperIO wake method */
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Method (SIOW, 1, NotSerialized)
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{
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/* Store wake status */
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PMFG = GPS2
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/* Disable wake on GPE */
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GPEE = Zero
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GPE0 = Zero
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GPE1 = Zero
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/* green LED normal */
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Local1 = LEDC
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Local1 &= 0xE0
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LEDC = (Local1 | 0x1E)
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Local1 = SWCC
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SWCC = (Local1 & 0xBF)
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}
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}
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@ -25,6 +25,8 @@
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#include <pc80/keyboard.h>
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#include <stdlib.h>
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#include <superio/conf_mode.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include "npcd378.h"
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@ -101,6 +103,53 @@ static void npcd378_init(struct device *dev)
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}
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}
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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static void npcd378_ssdt(struct device *dev)
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{
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struct resource *res;
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const char *scope = acpi_device_path(dev);
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if (!scope) {
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printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev));
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return;
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}
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switch (dev->path.pnp.device) {
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case NPCD378_PWR: {
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res = find_resource(dev, PNP_IDX_IO0);
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if (!res || !res->base) {
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printk(BIOS_ERR, "NPCD378: LDN%u IOBASE not set.\n",
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NPCD378_PWR);
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break;
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}
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acpigen_write_scope(scope);
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acpigen_write_name_integer("SWB", res->base);
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acpigen_write_name_integer("SWL", res->size);
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acpigen_pop_len(); /* pop scope */
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res = find_resource(dev, PNP_IDX_IO1);
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if (!res || !res->base) {
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printk(BIOS_ERR, "NPCD378: LDN%u IOBASE2 not set.\n",
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NPCD378_PWR);
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break;
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}
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acpigen_write_scope(scope);
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acpigen_write_name_integer("RNB", res->base);
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acpigen_write_name_integer("RNL", res->size);
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acpigen_pop_len(); /* pop scope */
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break;
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}
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}
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}
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static const char *npcd378_acpi_name(const struct device *dev)
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{
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return "SIO0";
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}
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#endif
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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@ -108,6 +157,10 @@ static struct device_operations ops = {
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.enable = pnp_alt_enable,
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.init = npcd378_init,
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.ops_pnp_mode = &pnp_conf_mode_8787_aa,
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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.acpi_fill_ssdt_generator = npcd378_ssdt,
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.acpi_name = npcd378_acpi_name,
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#endif
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};
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static struct pnp_info pnp_dev_info[] = {
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