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baytrail: Switch from ACPI mode to PCI mode for legacy support 

Most Baytrail based devices MMIO registers are reported in ACPI
space and the device's PCI config space is disabled. The PCI config
space is required for many "legacy" OSs that don't have the ACPI
driver loading mechanism. Depthcharge signals the legacy boot
path via the SMI 0xCC and the coreboot SMI handler can switch the
device specific registers to re-enable PCI config space.

BUG=chrome-os-partner:30836
BRANCH=None
TEST=Build and boot Rambi SeaBIOS.

Change-Id: I87248936e2a7e026f38c147bdf0df378e605e370
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: dbb9205ee22ffce44e965be51ae0bc62d4ca5dd4
Original-Change-Id: Ia5e54f4330eda10a01ce3de5aa4d86779d6e1bf9
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219801
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
Original-Tested-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/9459
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Marc Jones 2014-09-24 10:53:48 -06:00 committed by Stefan Reinauer
parent 1376b680c2
commit 9afc5c05f0
3 changed files with 61 additions and 0 deletions
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1
src/include/cpu/x86/smm.h
View File

@ -460,6 +460,7 @@ typedef struct {
#define APM_CNT_MBI_UPDATE 0xeb
#define APM_CNT_GNVS_UPDATE 0xea
#define APM_CNT_FINALIZE 0xcb
#define APM_CNT_LEGACY 0xcc
#define APM_STS 0xb3
/* SMI handler function prototypes */

1
src/soc/intel/baytrail/Makefile.inc
View File

@ -20,6 +20,7 @@ ramstage-y += chip.c
ramstage-y += gfx.c
ramstage-y += iosf.c
romstage-y += iosf.c
smm-y += iosf.c
ramstage-y += northcluster.c
ramstage-y += ramstage.c
ramstage-y += gpio.c

59
src/soc/intel/baytrail/smihandler.c
View File

@ -28,6 +28,7 @@
#include <halt.h>
#include <spi-generic.h>
#include <soc/iosf.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/nvs.h>
@ -250,6 +251,60 @@ static void finalize(void)
#endif
}
/*
* soc_legacy: A payload (Depthcharge) has indicated that the
* legacy payload (SeaBIOS) is being loaded. Switch devices that are
* in ACPI mode to PCI mode so that non-ACPI drivers may work.
*
*/
static void soc_legacy(void)
{
u32 reg32;
/* LPE Device */
if (gnvs->dev.lpe_en) {
reg32 = iosf_port58_read(LPE_PCICFGCTR1);
reg32 &=
~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN);
iosf_port58_write(LPE_PCICFGCTR1, reg32);
}
/* SCC Devices */
#define SCC_ACPI_MODE_DISABLE(name_) \
do { if (gnvs->dev.scc_en[SCC_NVS_ ## name_]) { \
reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \
reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \
iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \
} } while (0)
SCC_ACPI_MODE_DISABLE(MMC);
SCC_ACPI_MODE_DISABLE(SD);
SCC_ACPI_MODE_DISABLE(SDIO);
/* LPSS Devices */
#define LPSS_ACPI_MODE_DISABLE(name_) \
do { if (gnvs->dev.lpss_en[LPSS_NVS_ ## name_]) { \
reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \
reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \
iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \
} } while (0)
LPSS_ACPI_MODE_DISABLE(SIO_DMA1);
LPSS_ACPI_MODE_DISABLE(I2C1);
LPSS_ACPI_MODE_DISABLE(I2C2);
LPSS_ACPI_MODE_DISABLE(I2C3);
LPSS_ACPI_MODE_DISABLE(I2C4);
LPSS_ACPI_MODE_DISABLE(I2C5);
LPSS_ACPI_MODE_DISABLE(I2C6);
LPSS_ACPI_MODE_DISABLE(I2C7);
LPSS_ACPI_MODE_DISABLE(SIO_DMA2);
LPSS_ACPI_MODE_DISABLE(PWM1);
LPSS_ACPI_MODE_DISABLE(PWM2);
LPSS_ACPI_MODE_DISABLE(HSUART1);
LPSS_ACPI_MODE_DISABLE(HSUART2);
LPSS_ACPI_MODE_DISABLE(SPI);
}
static void southbridge_smi_apmc(void)
{
uint8_t reg8;
@ -303,6 +358,10 @@ static void southbridge_smi_apmc(void)
case APM_CNT_FINALIZE:
finalize();
break;
case APM_CNT_LEGACY:
soc_legacy();
break;
}
mainboard_smi_apmc(reg8);