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This patch corrects a coding error in the original implementation 

of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code
sets msr c001_102a bit 3 when bit 35 was intended.


Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2010-09-14 17:28:41 +00:00 committed by Marc Jones
parent 3f1d29c408
commit 9b0c690c09
1 changed files with 2 additions and 2 deletions
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4
src/cpu/amd/car/cache_as_ram.inc
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@ -129,8 +129,8 @@ CAR_FAM10_out:
/* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */
rdmsr
/* Set bit 35 to 1 in EAX */
bts $35, %eax
/* Set bit 35 to 1 in EAX:EDX */
bts $35-32, %edx
/* write back the modified register EDX:EAX to the MSR specified in ECX */
wrmsr