intel/i82801ix: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3809 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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@ -237,39 +237,35 @@ static void azalia_init(struct device *dev)
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u8 reg8;
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u32 reg32;
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#if CONFIG_MMCONF_SUPPORT
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// ESD
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reg32 = pci_mmio_read_config32(dev, 0x134);
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reg32 = pci_read_config32(dev, 0x134);
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reg32 &= 0xff00ffff;
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reg32 |= (2 << 16);
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pci_mmio_write_config32(dev, 0x134, reg32);
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pci_write_config32(dev, 0x134, reg32);
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// Link1 description
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reg32 = pci_mmio_read_config32(dev, 0x140);
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reg32 = pci_read_config32(dev, 0x140);
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reg32 &= 0xff00ffff;
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reg32 |= (2 << 16);
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pci_mmio_write_config32(dev, 0x140, reg32);
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pci_write_config32(dev, 0x140, reg32);
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// Port VC0 Resource Control Register
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reg32 = pci_mmio_read_config32(dev, 0x114);
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reg32 = pci_read_config32(dev, 0x114);
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reg32 &= 0xffffff00;
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reg32 |= 1;
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pci_mmio_write_config32(dev, 0x114, reg32);
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pci_write_config32(dev, 0x114, reg32);
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// VCi traffic class
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reg8 = pci_mmio_read_config8(dev, 0x44);
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reg8 = pci_read_config8(dev, 0x44);
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reg8 |= (7 << 0); // TC7
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pci_mmio_write_config8(dev, 0x44, reg8);
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pci_write_config8(dev, 0x44, reg8);
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// VCi Resource Control
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reg32 = pci_mmio_read_config32(dev, 0x120);
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reg32 = pci_read_config32(dev, 0x120);
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reg32 |= (1 << 31);
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reg32 |= (1 << 24); // VCi ID
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reg32 |= (0x80 << 0); // VCi map
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pci_mmio_write_config32(dev, 0x120, reg32);
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#else
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#error ICH9 Azalia required CONFIG_MMCONF_SUPPORT
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#endif
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pci_write_config32(dev, 0x120, reg32);
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/* Set Bus Master */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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@ -27,6 +27,10 @@
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#include <console/console.h>
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#include "i82801ix.h"
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#if !CONFIG_MMCONF_SUPPORT_DEFAULT
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#error ICH9 requires CONFIG_MMCONF_SUPPORT_DEFAULT
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#endif
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typedef struct southbridge_intel_i82801ix_config config_t;
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static void i82801ix_enable_device(device_t dev)
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@ -66,13 +70,9 @@ static void i82801ix_pcie_init(const config_t *const info)
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printk(BIOS_EMERG, "PCIe port 00:1c.%x", i);
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die(" is not listed in devicetree.\n");
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}
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#if CONFIG_MMCONF_SUPPORT
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reg32 = pci_mmio_read_config32(pciePort[i], 0x300);
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pci_mmio_write_config32(pciePort[i], 0x300, reg32 | (1 << 21));
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pci_mmio_write_config8(pciePort[i], 0x324, 0x40);
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#else
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#error "MMIO needed for ICH9 PCIe"
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#endif
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reg32 = pci_read_config32(pciePort[i], 0x300);
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pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21));
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pci_write_config8(pciePort[i], 0x324, 0x40);
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}
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if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) {
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@ -87,13 +87,9 @@ static void i82801ix_pcie_init(const config_t *const info)
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for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) {
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/* Only for the top disabled ports. */
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#if CONFIG_MMCONF_SUPPORT
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reg32 = pci_mmio_read_config32(pciePort[i], 0x300);
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reg32 = pci_read_config32(pciePort[i], 0x300);
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reg32 |= 0x3 << 16;
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pci_mmio_write_config32(pciePort[i], 0x300, reg32);
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#else
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#error "MMIO needed for ICH9 PCIe"
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#endif
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pci_write_config32(pciePort[i], 0x300, reg32);
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}
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/* Set slot implemented, slot number and slot power limits. */
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@ -56,23 +56,19 @@ static void pci_init(struct device *dev)
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reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
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pci_write_config32(dev, 0xe1, reg32);
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#if CONFIG_MMCONF_SUPPORT
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/* Set VC0 transaction class */
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reg32 = pci_mmio_read_config32(dev, 0x114);
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reg32 = pci_read_config32(dev, 0x114);
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reg32 &= 0xffffff00;
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reg32 |= 1;
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pci_mmio_write_config32(dev, 0x114, reg32);
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pci_write_config32(dev, 0x114, reg32);
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/* Mask completion timeouts */
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reg32 = pci_mmio_read_config32(dev, 0x148);
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reg32 = pci_read_config32(dev, 0x148);
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reg32 |= (1 << 14);
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pci_mmio_write_config32(dev, 0x148, reg32);
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pci_write_config32(dev, 0x148, reg32);
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/* Lock R/WO Correctable Error Mask. */
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pci_mmio_write_config32(dev, 0x154, pci_mmio_read_config32(dev, 0x154));
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#else
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#error "MMIO needed for ICH9 PCIe"
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#endif
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pci_write_config32(dev, 0x154, pci_read_config32(dev, 0x154));
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/* Clear errors in status registers */
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reg16 = pci_read_config16(dev, 0x06);
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@ -344,7 +344,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
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if (tco_sts & (1 << 8)) { // BIOSWR
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u8 bios_cntl;
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bios_cntl = pci_mmio_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
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bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
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if (bios_cntl & 1) {
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/* BWE is RW, so the SMI was caused by a
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@ -358,7 +358,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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pci_mmio_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
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} /* No else for now? */
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} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
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/* Handle TCO timeout */
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@ -501,7 +501,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
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u32 smi_sts;
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/* Update global variable pmbase */
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pmbase = pci_mmio_read_config16(PCI_DEV(0, 0x1f, 0), D31F0_PMBASE) & 0xfffc;
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pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), D31F0_PMBASE) & 0xfffc;
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/* We need to clear the SMI status registers, or we won't see what's
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* happening in the following calls.
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