code reformat, is the pirq table correct?
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -27,19 +27,18 @@
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static void hard_reset(void)
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{
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set_bios_reset();
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/* enable cf9 */
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pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
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/* reset */
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outb(0x0e, 0x0cf9);
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}
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static void soft_reset(void)
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{
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
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}
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/* enable cf9 */
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pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
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/* reset */
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outb(0x0e, 0x0cf9);
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}
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static void soft_reset(void)
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{
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
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}
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static void memreset_setup(void)
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{
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@ -48,8 +47,7 @@ static void memreset_setup(void)
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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else {
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} else {
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/* Ensure the CPU has controll of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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@ -123,61 +121,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#if 0
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static void enable_lapic(void)
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{
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msr_t msr;
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msr = rdmsr(0x1b);
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msr.hi &= 0xffffff00;
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msr.lo &= 0x000007ff;
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msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
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wrmsr(0x1b, msr);
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}
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static void stop_this_cpu(void)
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{
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unsigned apicid;
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apicid = apic_read(APIC_ID) >> 24;
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/* Send an APIC INIT to myself */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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/* Deassert the APIC INIT */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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/* If I haven't halted spin forever */
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for(;;) {
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hlt();
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}
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}
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#define PC87360_FDC 0x00
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#define PC87360_PP 0x01
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#define PC87360_SP2 0x02
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#define PC87360_SP1 0x03
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#define PC87360_SWC 0x04
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#define PC87360_KBCM 0x05
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#define PC87360_KBCK 0x06
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#define PC87360_GPIO 0x07
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#define PC87360_ACB 0x08
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#define PC87360_FSCM 0x09
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#define PC87360_WDT 0x0A
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static void pc87360_enable_serial(void)
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{
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pnp_set_logical_device(SIO_BASE, PC87360_SP1);
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pnp_set_enable(SIO_BASE, 1);
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pnp_set_iobase0(SIO_BASE, 0x3f8);
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}
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#endif
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#define FIRST_CPU 1
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#define SECOND_CPU 1
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#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
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@ -228,57 +171,30 @@ static void main(void)
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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setup_default_resource_map();
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needs_reset = setup_coherent_ht_domain();
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
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if (needs_reset) {
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print_info("ht reset -\r\n");
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soft_reset();
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}
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if (needs_reset) {
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print_info("ht reset -\r\n");
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soft_reset();
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}
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#if 0
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print_pci_devices();
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#endif
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enable_smbus();
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#if 0
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dump_spd_registers(&cpu[0]);
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#endif
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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#if 1
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dump_pci_devices();
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#endif
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#if 0
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dump_pci_devices();
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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#endif
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/* Check all of memory */
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#if 0
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msr_t msr;
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msr = rdmsr(TOP_MEM);
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print_debug("TOP_MEM: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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#endif
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#if 0
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ram_check(0x00000000, msr.lo);
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#endif
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#if 0
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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#if TOTAL_CPUS > 1
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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#endif
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};
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int i;
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for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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}
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#endif
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}
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