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sb/intel/i82371eb: Add PIIX4 definitions 

These new definitions will be used by two other changes.

Change-Id: I242244c444f36af188c871dce037a7a9250206cd
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38367
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui 2020-01-11 13:49:59 -05:00 committed by Patrick Georgi
parent f555a58abc
commit 9b4b33ac37
1 changed files with 5 additions and 0 deletions
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5
src/southbridge/intel/i82371eb/i82371eb.h
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@ -40,6 +40,11 @@ int smbus_read_byte(u8 device, u8 address);
#define XBCS 0x4e /* X-Bus chip select register */ #define XBCS 0x4e /* X-Bus chip select register */
#define GENCFG 0xb0 /* General configuration register */ #define GENCFG 0xb0 /* General configuration register */
#define GPO2223 (1<<28) /* GPO22/23 */
#define RTCCFG 0xcb /* Real time clock configuration register */
#define RTC_POS_DECODE (1<<5)
#define UPPER_RAM_EN (1<<2)
#define RTC_ENABLE (1<<0)
/* IDE */ /* IDE */
#define IDETIM_PRI 0x40 /* IDE timing register, primary channel */ #define IDETIM_PRI 0x40 /* IDE timing register, primary channel */