mb/intel/adlrvp: Add ADL-P ramstage mainboard code
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for ramstage(ec.c, mainboard.c) 4. Add smihandler.c for SMM 5. Add devicetree changes as below - USB OC PIN programing - GPE configuration - SATA port mapping - LPSS configuration - Audio configuration - IA common SoC configuration - EDP configuration - TCSS USB configuration - Enable S0ix TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till depthcharge payload. Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik
Patrick Georgi
parent
522ba1ba27
commit
9b4f221026
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@ -11,7 +11,12 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += romstage_fsp_params.c
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romstage-y += board_id.c
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smm-y += smihandler.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += ec.c
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ramstage-y += mainboard.c
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ramstage-y += board_id.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <baseboard/ec.h>
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void mainboard_ec_init(void)
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{
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const struct google_chromeec_event_info info = {
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.log_events = MAINBOARD_EC_LOG_EVENTS,
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.sci_events = MAINBOARD_EC_SCI_EVENTS,
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.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
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.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
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.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
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};
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google_chromeec_events_init(&info, acpi_is_wakeup_s3());
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}
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@ -0,0 +1,40 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <ec/ec.h>
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#include <soc/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <smbios.h>
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#include <stdint.h>
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#include <string.h>
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#include "board_id.h"
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const char *smbios_system_sku(void)
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{
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static char sku_str[7] = "";
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uint8_t sku_id = get_board_id();
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snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id);
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return sku_str;
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}
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static void mainboard_init(void *chip_info)
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{
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variant_configure_gpio_pads();
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if (CONFIG(EC_GOOGLE_CHROMEEC))
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mainboard_ec_init();
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <cpu/x86/smm.h>
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#include <ec/google/chromeec/smm.h>
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#include <intelblocks/smihandler.h>
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#include <baseboard/ec.h>
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void mainboard_smi_espi_handler(void)
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{
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if (!CONFIG(EC_GOOGLE_CHROMEEC))
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return;
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chromeec_smi_process_events();
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}
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void mainboard_smi_sleep(u8 slp_typ)
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{
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if (!CONFIG(EC_GOOGLE_CHROMEEC))
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return;
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chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
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}
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int mainboard_smi_apmc(u8 apmc)
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{
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if (CONFIG(EC_GOOGLE_CHROMEEC))
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chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
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return 0;
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}
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@ -3,3 +3,5 @@
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bootblock-y += early_gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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@ -4,6 +4,34 @@ chip soc/intel/alderlake
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device lapic 0 on end
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end
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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# FSP configuration
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# Enable Speed Shift Technology/HWP support
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register "speed_shift_enable" = "1"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2
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register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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@ -41,6 +69,101 @@ chip soc/intel/alderlake
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# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
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register "PcieClkSrcUsage[6]" = "0xff"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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}"
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register "SataPortsDevSlp" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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}"
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# Enable EDP in PortA
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register "DdiPortAConfig" = "1"
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register "DdiPortBConfig" = "1"
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# TCSS USB3
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register "TcssAuxOri" = "0"
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register "s0ix_enable" = "1"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoPci,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoGSpiCsState" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# HD Audio
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register "PchHdaDspEnable" = "1"
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register "PchHdaAudioLinkHdaEnable" = "0"
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register "PchHdaAudioLinkDmicEnable[0]" = "1"
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register "PchHdaAudioLinkDmicEnable[1]" = "1"
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register "PchHdaAudioLinkSndwEnable[0]" = "1"
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register "PchHdaAudioLinkSndwEnable[1]" = "1"
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# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
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register "PchHdaIDispLinkTmode" = "2"
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# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
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register "PchHdaIDispLinkFrequency" = "4"
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# Not disconnected/enumerable
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register "PchHdaIDispCodecDisconnect" = "0"
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# Intel Common SoC Config
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Graphics
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@ -107,7 +230,7 @@ chip soc/intel/alderlake
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device pci 17.0 on end # SATA
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device pci 19.0 off end # I2C4
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device pci 19.1 on end # I2C5
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device pci 19.2 on end # UART2
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device pci 19.2 off end # UART2
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device pci 1c.0 on end # RP1
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device pci 1c.1 off end # RP2
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device pci 1c.2 off end # RP3
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@ -120,9 +243,9 @@ chip soc/intel/alderlake
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device pci 1d.1 off end # RP10
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device pci 1d.2 off end # RP11
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device pci 1d.3 off end # RP12
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device pci 1e.0 off end # UART0
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device pci 1e.0 on end # UART0
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device pci 1e.1 off end # UART1
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device pci 1e.2 off end # GSPI0
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device pci 1e.2 on end # GSPI0
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device pci 1e.3 off end # GSPI1
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device pci 1f.0 on end # eSPI
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device pci 1f.1 on end # P2SB
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@ -0,0 +1,297 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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/* Pad configuration in ramstage*/
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static const struct pad_config gpio_table[] = {
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/* SSD1_PWREN CPU SSD1 */
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PAD_CFG_GPO(GPP_D14, 1, PLTRST),
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/* SSD1_RESET CPU SSD1 */
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PAD_CFG_GPO(GPP_F20, 1, PLTRST),
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/* BT_RF_KILL_N */
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PAD_CFG_GPO(GPP_A13, 1, PLTRST),
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/* WLAN RST# */
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PAD_CFG_GPO(GPP_H2, 1, PLTRST),
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/* WIFI_WAKE_N */
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PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT),
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/* x4 PCIE slot1 PWREN */
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PAD_CFG_GPO(GPP_H17, 0, PLTRST),
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/* x4 PCIE slot 1 RESET */
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PAD_CFG_GPO(GPP_F10, 1, PLTRST),
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/* Retimer Force Power */
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PAD_CFG_GPO(GPP_E4, 0, PLTRST),
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/* PEG Slot RST# */
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PAD_CFG_GPO(GPP_B2, 1, PLTRST),
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/* M.2 SSD_2 Reset */
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PAD_CFG_GPO(GPP_H0, 1, PLTRST),
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/* CAM1-IRQ */
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PAD_CFG_GPO(GPP_B23, 1, PLTRST),
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/* CAM_STROBE */
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PAD_CFG_GPO(GPP_B18, 0, PLTRST),
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/* Audio Codec INT N */
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PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
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/* TCH PAD Power EN */
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PAD_CFG_GPO(GPP_F7, 1, PLTRST),
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/* THC1 SPI2 RST# */
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PAD_CFG_GPO(GPP_F17, 1, PLTRST),
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/* THC1_SPI2_INTB */
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PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
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/* THC1_SPI2_INTB */
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PAD_CFG_GPI(GPP_E17, NONE, PLTRST),
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/* EC_SMI_N */
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PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, NONE),
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/* EC_SLP_S0_CS_N */
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PAD_CFG_GPO(GPP_F9, 1, PLTRST),
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/* WIFI RF KILL */
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PAD_CFG_GPO(GPP_E3, 1, PLTRST),
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/* DISP_AUX_N_BIAS_GPIO */
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PAD_CFG_GPO(GPP_E23, 1, PLTRST),
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/* WWAN WAKE N*/
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PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
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/* WWAN_DISABLE_N */
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PAD_CFG_GPO(GPP_D15, 1, PLTRST),
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/* WWAN_RST# */
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PAD_CFG_GPO(GPP_E10, 1, PLTRST),
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/* WWAN_PWR_EN */
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PAD_CFG_GPO(GPP_E13, 1, DEEP),
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/* WWAN_PERST# */
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PAD_CFG_GPO(GPP_C5, 1, PLTRST),
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/* PEG_SLOT_WAKE_N */
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PAD_CFG_GPI(GPP_A20, NONE, PLTRST),
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/* UART_BT_WAKE_N */
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PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT),
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/* CAM CONN1 CLKEN */
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PAD_CFG_GPO(GPP_H15, 1, PLTRST),
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/* CPU SSD2 PWREN */
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PAD_CFG_GPO(GPP_C2, 1, PLTRST),
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/* CPU SSD2 RST# */
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PAD_CFG_GPO(GPP_H1, 1, PLTRST),
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/* Sata direct Power */
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PAD_CFG_GPO(GPP_B4, 1, PLTRST),
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/* THC0 SPI1 CLK */
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PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2),
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/* THC0 SPI1 IO 1 */
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PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2),
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/* THC0 SPI1 IO 2 */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
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/* THC0 SPI IO 3 */
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PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2),
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/* THC1 SPI1 RSTB */
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PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2),
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/* UART_RX(1) */
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
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/* UART_RX(2) */
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* UART_RX(4) */
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PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),
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/* UART_RX(5) */
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PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1),
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/* UART_RX(6) */
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PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1),
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/* UART_TX(1) */
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
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/* UART_TX(2) */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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/* UART_TX(4) */
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PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1),
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/* UART_TX(5) */
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PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1),
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/* UART_TX(6) */
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PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1),
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/* UART_RTS(1) */
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PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
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/* UART_RTS(2) */
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PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
|
||||
/* UART_RTS(4) */
|
||||
PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),
|
||||
/* UART_RTS(5) */
|
||||
PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1),
|
||||
/* UART_RTS(6) */
|
||||
PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1),
|
||||
|
||||
/* UART_CTS(1) */
|
||||
PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
|
||||
/* UART_CTS(2) */
|
||||
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
|
||||
/* UART_CTS(4) */
|
||||
PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),
|
||||
/* UART_CTS(5) */
|
||||
PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1),
|
||||
/* UART_CTS(6) */
|
||||
PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1),
|
||||
|
||||
/* SPI_MOSI(1) */
|
||||
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
|
||||
/* SPI_MOSI(2) */
|
||||
PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
|
||||
|
||||
/* SPI_MIS0(0) */
|
||||
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
|
||||
/* SPI_MIS0(1) */
|
||||
PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
|
||||
/* SPI_MIS0(2) */
|
||||
PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
|
||||
|
||||
/* SPI_CLK(0) */
|
||||
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
|
||||
/* SPI_CLK(1) */
|
||||
PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
|
||||
/* SPI_CLK(2) */
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
|
||||
|
||||
/* SPI_CS(0, 0) */
|
||||
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
|
||||
/* SPI_CS(0, 1) */
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
/* SPI_CS(1, 0) */
|
||||
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
|
||||
/* SPI_CS(2, 0) */
|
||||
PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2),
|
||||
|
||||
/* I2C_SCL(0) */
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
/* I2C_SCL(1) */
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
/* I2C_SCL(2) */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* I2C_SCL(3) */
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
/* I2C_SCL(5) */
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
/* I2C_SCL(6) */
|
||||
PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1),
|
||||
/* I2C_SCL(7) */
|
||||
PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1),
|
||||
|
||||
/* I2C_SDA(0) */
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
/* I2C_SDA(1) */
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
/* I2C_SDA(2) */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
/* I2C_SDA(3) */
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
/* I2C_SDA(5) */
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
/* I2C_SDA(6) */
|
||||
PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1),
|
||||
/* I2C_SDA(7) */
|
||||
PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1),
|
||||
|
||||
/* I2S0_SCLK */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
|
||||
/* I2S0_SFRM */
|
||||
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
|
||||
/* I2S0_TXD */
|
||||
PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
|
||||
/* I2S0_RXD */
|
||||
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
|
||||
|
||||
/* I2S1_SCLK */
|
||||
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
|
||||
/* I2S1_SFRM */
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
|
||||
/* I2S1_TXD */
|
||||
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
|
||||
/* I2S1_RXD */
|
||||
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
|
||||
|
||||
/* I2S2_SCLK */
|
||||
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
|
||||
/* I2S2_SFRM */
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
/* I2S2_TXD */
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
/* I2S2_RXD */
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
|
||||
/* I2S_MCLK1_OUT */
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
/* I2S_MCLK2_INOUT */
|
||||
PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
|
||||
|
||||
/* SNDW1_CLK */
|
||||
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
|
||||
/* SNDW1_DATA */
|
||||
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
|
||||
/* SNDW2_CLK */
|
||||
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
|
||||
/* SNDW2_DATA */
|
||||
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
|
||||
/* SNDW3_CLK */
|
||||
PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
|
||||
/* SNDW3_DATA */
|
||||
PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
|
||||
/* SNDW4_CLK */
|
||||
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1),
|
||||
/* SNDW4_DATA */
|
||||
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1),
|
||||
|
||||
/* SMB_CLK */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
/* SMB_DATA */
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
|
||||
/* SATADevSlpPin to GPIO pin mapping */
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
/* SATA DIRECT DEVSLP*/
|
||||
PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5),
|
||||
|
||||
/* SATA LED pin */
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
|
||||
/* USB2 OC0 pins */
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
/* USB2 OC1 pins */
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
/* USB2 OC2 pins */
|
||||
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
|
||||
/* USB2 OC3 pins */
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
|
||||
/* GPIO pin for PCIE SRCCLKREQB */
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
|
||||
/* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
|
||||
|
||||
/* IMGCLKOUT */
|
||||
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
void variant_configure_gpio_pads(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __BASEBOARD_EC_H__
|
||||
#define __BASEBOARD_EC_H__
|
||||
|
||||
#include <ec/ec.h>
|
||||
#include <ec/google/chromeec/ec_commands.h>
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#define MAINBOARD_EC_SCI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
|
||||
|
||||
#define MAINBOARD_EC_SMI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
|
||||
|
||||
/* EC can wake from S5 with lid or power button */
|
||||
#define MAINBOARD_EC_S5_WAKE_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
|
||||
|
||||
/*
|
||||
* EC can wake from S3 with lid or power button or key press or
|
||||
* mode change event.
|
||||
*/
|
||||
#define MAINBOARD_EC_S3_WAKE_EVENTS \
|
||||
(MAINBOARD_EC_S5_WAKE_EVENTS |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
|
||||
|
||||
#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
|
||||
|
||||
/* Log EC wake events plus EC shutdown events */
|
||||
#define MAINBOARD_EC_LOG_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
|
||||
|
||||
/*
|
||||
* ACPI related definitions for ASL code.
|
||||
*/
|
||||
|
||||
/* Enable EC backed ALS device in ACPI */
|
||||
#define EC_ENABLE_ALS_DEVICE
|
||||
|
||||
/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
|
||||
#define EC_ENABLE_SYNC_IRQ
|
||||
|
||||
/* Enable EC backed PD MCU device in ACPI */
|
||||
#define EC_ENABLE_PD_MCU_DEVICE
|
||||
|
||||
/* Enable LID switch and provide wake pin for EC */
|
||||
#define EC_ENABLE_LID_SWITCH
|
||||
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
|
||||
|
||||
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
|
||||
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
|
||||
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
|
||||
|
||||
#endif /* __BASEBOARD_EC_H__ */
|
||||
|
|
@ -20,7 +20,8 @@ enum adl_boardid {
|
|||
/* The next set of functions return the gpio table and fill in the number of
|
||||
* entries for each table. */
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num);
|
||||
|
||||
/* Functions to configure GPIO as per variant schematics */
|
||||
void variant_configure_gpio_pads(void);
|
||||
void variant_configure_early_gpio_pads(void);
|
||||
|
||||
size_t variant_memory_sku(void);
|
||||
|
|
|
|||
Loading…
Reference in New Issue