soc/intel/cannonlake: add *spi.c files to make

Adds spi.c and gspi.c to verstage.

Change-Id: I363d9aafa989c5a7a0b36ad9edf1c70a75604d28
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/cannonlake/Makefile.inc

@@ -44,6 +44,9 @@ postcar-y += pmutil.c
 postcar-y += spi.c
 postcar-$(CONFIG_UART_DEBUG) += uart.c
 
+verstage-y += gspi.c
+verstage-y += spi.c
+
 CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake