doc/mb/upsquared: Add documentation
This patch adds documentation about the UP² mainboard and the IFWI used by Apollolake platform. Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Felix Singer
Patrick Rudolph
parent
9065657957
commit
9b7e990d18
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<tspan x="460" y="-20">40 pin GPIO header</tspan>
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<tspan x="520" y="-175.575">GND</tspan>
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<tspan x="560" y="-203.575">UART1</tspan>
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<tspan x="560" y="-187.575">TX</tspan>
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<tspan x="600" y="-183.575">UART1</tspan>
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<tspan x="600" y="-167.575">RX</tspan>
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</text>
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</text>
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</text>
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</text>
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</text>
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<tspan x="330" y="34.425">11</tspan>
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</text>
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<tspan x="370" y="74.425">10</tspan>
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<tspan x="480" y="152.425">1.8V</tspan>
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|
||||
<tspan x="440" y="164.238">#CS</tspan>
|
||||
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</svg>
|
||||
|
After Width: | Height: | Size: 9.6 KiB |
|
|
@ -7,6 +7,12 @@
|
|||
### Bottom
|
||||
![][overview_bottom]
|
||||
|
||||
* **Legend**
|
||||
* [BLUE][header_cn16_link]: UART0 / USB connector
|
||||
* [GREEN][header_gpio_link]: UART1 / GPIO header
|
||||
* [RED][header_cn22_link]: SPI header
|
||||
* YELLOW: Indicates pin 1
|
||||
|
||||
## Mainboard components
|
||||
### Platform
|
||||
```eval_rst
|
||||
|
|
@ -46,6 +52,79 @@
|
|||
+---------------------+------------+
|
||||
```
|
||||
|
||||
### Debugging
|
||||
#### UART0 (CN16)
|
||||
This connector is located on the **bottom** side (see [here][overview_bottom_link]).
|
||||
![][header_cn16]
|
||||
|
||||
|
||||
#### UART1 (GPIO header)
|
||||
The GPIO header is located on the **bottom** side (see [here][overview_bottom_link]).
|
||||
![][header_gpio]
|
||||
|
||||
## Building and flashing coreboot
|
||||
### Using the SPI header
|
||||
The SPI header is located on the **bottom** side (see [here][overview_bottom_link]).
|
||||
![][header_cn22]
|
||||
|
||||
### Preperations
|
||||
In order to build coreboot, it's neccessary to extract some files from the vendor firmware. Make sure that you have a fully working dump.
|
||||
```bash
|
||||
[upsquared]$ ls
|
||||
firmware_vendor.rom
|
||||
```
|
||||
|
||||
```bash
|
||||
[upsquared]$ mkdir extracted && cd extracted
|
||||
[extracted]$ ifdtool -x ../firmware_vendor.rom
|
||||
File ../firmware_vendor.rom is 16777216 bytes
|
||||
Peculiar firmware descriptor, assuming Ibex Peak compatibility.
|
||||
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
|
||||
Flash Region 1 (BIOS): 00001000 - 00efefff
|
||||
Flash Region 2 (Intel ME): 07fff000 - 00000fff (unused)
|
||||
Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
|
||||
Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
|
||||
Flash Region 5 (Reserved): 00eff000 - 00ffefff
|
||||
Flash Region 6 (Reserved): 07fff000 - 00000fff (unused)
|
||||
Flash Region 7 (Reserved): 07fff000 - 00000fff (unused)
|
||||
Flash Region 8 (EC): 07fff000 - 00000fff (unused)
|
||||
```
|
||||
|
||||
```bash
|
||||
flashregion_0_flashdescriptor.bin
|
||||
flashregion_1_bios.bin
|
||||
flashregion_5_reserved.bin
|
||||
```
|
||||
|
||||
### Clean up
|
||||
```bash
|
||||
[coreboot]$ make distclean
|
||||
```
|
||||
|
||||
### Configuring
|
||||
```bash
|
||||
[coreboot]$ touch .config
|
||||
[coreboot]$ ./util/scripts/config --enable VENDOR_UP
|
||||
[coreboot]$ ./util/scripts/config --enable BOARD_UP_SQUARED
|
||||
[coreboot]$ ./util/scripts/config --enable NEED_IFWI
|
||||
[coreboot]$ ./util/scripts/config --enable HAVE_IFD_BIN
|
||||
[coreboot]$ ./util/scripts/config --set-str IFWI_FILE_NAME "<flashregion_1_bios.bin>"
|
||||
[coreboot]$ ./util/scripts/config --set-str IFD_BIN_PATH "<flashregion_0_flashdescriptor.bin>"
|
||||
[coreboot]$ make olddefconfig
|
||||
```
|
||||
|
||||
### Building
|
||||
```bash
|
||||
[coreboot]$ make
|
||||
```
|
||||
|
||||
Now you should have a working and ready to use coreboot build at `build/coreboot.rom`.
|
||||
|
||||
### Flashing
|
||||
```bash
|
||||
[coreboot]$ flashrom -p <your_programmer> -w build/coreboot.rom
|
||||
```
|
||||
|
||||
## Board status
|
||||
### Working
|
||||
- bootblock, romstage, ramstage
|
||||
|
|
@ -78,22 +157,13 @@
|
|||
- mini PCIe
|
||||
- flashing with flashrom internally using Linux
|
||||
|
||||
## Building and flashing coreboot
|
||||
### Building
|
||||
|
||||
```bash
|
||||
make distclean
|
||||
touch .config
|
||||
./util/scripts/config --enable VENDOR_UP
|
||||
./util/scripts/config --enable BOARD_UP_SQUARED
|
||||
./util/scripts/config --enable NEED_IFWI
|
||||
./util/scripts/config --enable HAVE_IFD_BIN
|
||||
./util/scripts/config --set-str IFWI_FILE_NAME "<path_to_your_bios_region>"
|
||||
./util/scripts/config --set-str IFD_BIN_PATH "<path_to_your_ifd_region>"
|
||||
make olddefconfig
|
||||
```
|
||||
|
||||
### Flashing
|
||||
|
||||
[header_cn16]: header_cn16_10pin_uart0.svg
|
||||
[header_cn16_link]: #uart0-cn16
|
||||
[header_cn22]: header_cn22_12pin_spi.svg
|
||||
[header_cn22_link]: #using-the-spi-header
|
||||
[header_gpio]: header_40pin_gpio_uart1.svg
|
||||
[header_gpio_link]: #uart1-gpio-header
|
||||
[overview_top]: top.jpg
|
||||
[overview_bottom]: bottom.jpg
|
||||
[overview_bottom_link]: #bottom
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -0,0 +1,122 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
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<svg width="38cm" height="18cm" viewBox="118 98 744 344" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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<tspan x="240" y="274.425">IFWI</tspan>
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||||
<g>
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<tspan x="350" y="414.425">FMAP</tspan>
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<tspan x="490" y="414.425">CONSOLE</tspan>
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<tspan x="620" y="414.425">COREBOOT(CBFS)</tspan>
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<tspan x="770" y="414.425">BIOS_UNUSABLE</tspan>
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<tspan x="410" y="414.425">MRC</tspan>
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</g>
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<text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490" y="274.425">
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<tspan x="490" y="274.425">OBB</tspan>
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</text>
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<g>
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<polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495,311 490,301 485,311 "/>
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</g>
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<g>
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<path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 840 380 C 840,300 490,360 490,311"/>
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<polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495,311 490,301 485,311 "/>
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<g>
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<rect style="fill: #ffffff" x="120" y="380" width="60" height="60"/>
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<rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="120" y="380" width="60" height="60"/>
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</g>
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<text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="150" y="414.425">
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<tspan x="150" y="414.425">TXE</tspan>
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</text>
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<tspan x="240" y="414.425">BOOTBLOCK</tspan>
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</text>
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</g>
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<g>
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<path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 120 380 C 120,320 240,360 240,311"/>
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<polygon style="fill: #000000" points="245,311 240,301 235,311 "/>
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<polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="245,311 240,301 235,311 "/>
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</g>
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</svg>
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|
After Width: | Height: | Size: 7.3 KiB |
|
|
@ -0,0 +1,17 @@
|
|||
# Apollolake
|
||||
## SPI flash layout
|
||||
|
||||
![][apl_flash_layout]
|
||||
|
||||
With Apollolake Intel invented another flash layout for x86 firmware called IFWI (Intel FirmWare Image).
|
||||
|
||||
Usually on x86 platforms the bootblock is stored at the end of the bios region
|
||||
and the Intel ME / TXE has its own IFD region. On Apollolake both have been
|
||||
moved into the IFWI region, which is a subregion of "BIOS", since it allows to
|
||||
store multiple firmware components.
|
||||
|
||||
The IFWI region can be manipulated by `ifwitool`.
|
||||
|
||||
[apl_flash_layout]: flash_layout.svg
|
||||
|
||||
|
||||
|
|
@ -9,3 +9,4 @@ This section contains documentation about coreboot on specific Intel SOCs.
|
|||
- [Ice Lake/9th Gen Core-i series](icelake/index.md)
|
||||
- [MP Initialization](mp_init/mp_init.md)
|
||||
- [Firmware Interface Table](fit.md)
|
||||
- [Apollolake](apollolake/index.md)
|
||||
|
|
|
|||
Loading…
Reference in New Issue