diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index ea92b31324..520c244fbf 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -135,14 +135,22 @@ static void request_ram_repair(void)
 
 	printk(BIOS_DEBUG, "Requesting RAM repair.\n");
 
+	stopwatch_init(&sw);
+
+	/* Perform cluster 0 ram repair */
 	reg = read32(&flow->ram_repair);
 	reg |= req;
 	write32(reg, &flow->ram_repair);
-
-	stopwatch_init(&sw);
 	while ((read32(&flow->ram_repair) & sts) != sts)
 		;
 
+	/* Perform cluster 1 ram repair */
+	reg = read32(&flow->ram_repair_cluster1);
+	reg |= req;
+	write32(reg, &flow->ram_repair_cluster1);
+	while ((read32(&flow->ram_repair_cluster1) & sts) != sts)
+		;
+
 	printk(BIOS_DEBUG, "RAM repair complete in %ld usecs.\n",
 		stopwatch_duration_usecs(&sw));
 }
diff --git a/src/soc/nvidia/tegra132/include/soc/flow.h b/src/soc/nvidia/tegra132/include/soc/flow.h
index 01dbc14208..e0cf495651 100644
--- a/src/soc/nvidia/tegra132/include/soc/flow.h
+++ b/src/soc/nvidia/tegra132/include/soc/flow.h
@@ -35,8 +35,14 @@ struct flow_ctlr {
 	u32 cpu_pwr_csr;	/* offset 0x38 */
 	u32 mpid;		/* offset 0x3c */
 	u32 ram_repair;		/* offset 0x40 */
+	u32 flow_dbg_sel;	/* offset 0x44 */
+	u32 flow_dbg_cnt0;	/* offset 0x48 */
+	u32 flow_dbg_cnt1;	/* offset 0x4c */
+	u32 flow_dbg_qual;	/* offset 0x50 */
+	u32 flow_ctlr_spare;	/* offset 0x54 */
+	u32 ram_repair_cluster1;/* offset 0x58 */
 };
-check_member(flow_ctlr, ram_repair, 0x40);
+check_member(flow_ctlr, ram_repair_cluster1, 0x58);
 
 enum {
 	FLOW_MODE_SHIFT = 29,