sandybridge: Native gfx init.
Change-Id: I07590086ffe3b1d068fa6ae6b156039cc2e55893 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6755 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Vladimir Serbinenko
parent
9f2dae4ec0
commit
9ba922f8bd
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@ -55,6 +55,10 @@ config IVYBRIDGE_LVDS
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bool
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default n
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config SANDYBRIDGE_LVDS
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bool
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default n
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config MRC_CACHE_SIZE
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hex
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depends on !CHROMEOS
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@ -21,6 +21,7 @@ ramstage-y += ram_calc.c
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ramstage-y += northbridge.c
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ramstage-y += gma.c
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ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c
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ramstage-$(CONFIG_SANDYBRIDGE_LVDS) += gma_sandybridge_lvds.c
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ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
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ramstage-y += mrccache.c
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@ -0,0 +1,558 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013, 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 or (at your option)
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* any later version of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <string.h>
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#include <drivers/intel/gma/edid.h>
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#include <drivers/intel/gma/i915.h>
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#include <drivers/intel/gma/intel_bios.h>
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#include "gma.h"
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#include "chip.h"
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#include <pc80/vga.h>
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#include <pc80/vga_io.h>
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#include <device/pci_def.h>
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#include <device/pci_rom.h>
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#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
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static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf,
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void *vbt)
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{
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struct vbt_header *head = vbt;
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struct bdb_header *bdb_head;
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struct bdb_general_features *genfeat;
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u8 *ptr;
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memset(head, 0, sizeof (*head));
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memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20);
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head->version = 100;
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head->header_size = sizeof (*head);
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head->bdb_offset = sizeof (*head);
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bdb_head = (struct bdb_header *) (head + 1);
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memset(bdb_head, 0, sizeof (*bdb_head));
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memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16);
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bdb_head->version = 0xa8;
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bdb_head->header_size = sizeof (*bdb_head);
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ptr = (u8 *) (bdb_head + 1);
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ptr[0] = BDB_GENERAL_FEATURES;
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ptr[1] = sizeof (*genfeat);
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ptr[2] = sizeof (*genfeat) >> 8;
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ptr += 3;
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genfeat = (struct bdb_general_features *) ptr;
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memset(genfeat, 0, sizeof (*genfeat));
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genfeat->panel_fitting = 3;
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genfeat->flexaim = 1;
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genfeat->download_ext_vbt = 1;
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genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock;
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genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz;
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genfeat->rsvd10 = 0x4;
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genfeat->legacy_monitor_detect = 1;
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genfeat->int_crt_support = 1;
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genfeat->dp_ssc_enb = 1;
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ptr += sizeof (*genfeat);
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bdb_head->bdb_size = ptr - (u8 *)bdb_head;
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head->vbt_size = ptr - (u8 *)head;
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head->vbt_checksum = 0;
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return ptr - (u8 *)head;
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}
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static void train_link(u32 mmio)
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{
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/* Clear interrupts. */
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write32(mmio + DEIIR, 0xffffffff);
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write32(mmio + 0xf000c, 0x2040);
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write32(mmio + 0xf000c, 0x2050);
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write32(mmio + 0x60100, 0x44000);
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write32(mmio + 0xf000c, 0x22050);
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mdelay(1);
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write32(mmio + 0x000f0018, 0x0000008ff);
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write32(mmio + 0x000f1018, 0x0000008ff);
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write32(mmio + 0x000f000c, 0x001a2050);
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write32(mmio + 0x00060100, 0x001c4000);
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write32(mmio + 0x00060100, 0x801c4000);
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write32(mmio + 0x000f000c, 0x801a2050);
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write32(mmio + 0x00060100, 0x801c4000);
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write32(mmio + 0x000f000c, 0x801a2050);
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mdelay(1);
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read32(mmio + 0x000f0014); // = 0x00000100
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write32(mmio + 0x000f0014, 0x00000100);
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write32(mmio + 0x00060100, 0x901c4000);
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write32(mmio + 0x000f000c, 0x801a2150);
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mdelay(1);
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read32(mmio + 0x000f0014); // = 0x00000600
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}
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static void power_port(u32 mmio)
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{
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read32(mmio + 0x000e1100); // = 0x00000000
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write32(mmio + 0x000e1100, 0x00000000);
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write32(mmio + 0x000e1100, 0x00010000);
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read32(mmio + 0x000e1100); // = 0x00010000
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read32(mmio + 0x000e1100); // = 0x00010000
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read32(mmio + 0x000e1100); // = 0x00000000
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write32(mmio + 0x000e1100, 0x00000000);
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read32(mmio + 0x000e1100); // = 0x00000000
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read32(mmio + 0x000e4200); // = 0x0000001c
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write32(mmio + 0x000e4210, 0x8004003e);
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write32(mmio + 0x000e4214, 0x80060002);
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write32(mmio + 0x000e4218, 0x01000000);
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read32(mmio + 0x000e4210); // = 0x5144003e
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write32(mmio + 0x000e4210, 0x5344003e);
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read32(mmio + 0x000e4210); // = 0x0144003e
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write32(mmio + 0x000e4210, 0x8074003e);
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read32(mmio + 0x000e4210); // = 0x5144003e
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read32(mmio + 0x000e4210); // = 0x5144003e
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write32(mmio + 0x000e4210, 0x5344003e);
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read32(mmio + 0x000e4210); // = 0x0144003e
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write32(mmio + 0x000e4210, 0x8074003e);
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read32(mmio + 0x000e4210); // = 0x5144003e
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read32(mmio + 0x000e4210); // = 0x5144003e
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write32(mmio + 0x000e4210, 0x5344003e);
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read32(mmio + 0x000e4210); // = 0x0144003e
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write32(mmio + 0x000e4210, 0x8074003e);
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read32(mmio + 0x000e4210); // = 0x5144003e
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read32(mmio + 0x000e4210); // = 0x5144003e
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write32(mmio + 0x000e4210, 0x5344003e);
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write32(mmio + 0x000e4f00, 0x0100030c);
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write32(mmio + 0x000e4f04, 0x00b8230c);
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write32(mmio + 0x000e4f08, 0x06f8930c);
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write32(mmio + 0x000e4f0c, 0x09f8e38e);
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write32(mmio + 0x000e4f10, 0x00b8030c);
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write32(mmio + 0x000e4f14, 0x0b78830c);
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write32(mmio + 0x000e4f18, 0x0ff8d3cf);
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write32(mmio + 0x000e4f1c, 0x01e8030c);
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write32(mmio + 0x000e4f20, 0x0ff863cf);
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write32(mmio + 0x000e4f24, 0x0ff803cf);
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write32(mmio + 0x000c4030, 0x00001000);
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read32(mmio + 0x000c4000); // = 0x00000000
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write32(mmio + 0x000c4030, 0x00001000);
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read32(mmio + 0x000e1150); // = 0x0000001c
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write32(mmio + 0x000e1150, 0x0000089c);
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write32(mmio + 0x000fcc00, 0x01986f00);
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write32(mmio + 0x000fcc0c, 0x01986f00);
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write32(mmio + 0x000fcc18, 0x01986f00);
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write32(mmio + 0x000fcc24, 0x01986f00);
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read32(mmio + 0x000c4000); // = 0x00000000
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read32(mmio + 0x000e1180); // = 0x40000002
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}
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int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
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u32 physbase, u16 piobase, u32 mmio, u32 lfb)
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{
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int i;
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u8 edid_data[128];
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struct edid edid;
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u32 hactive, vactive, right_border, bottom_border;
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int hpolarity, vpolarity;
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u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
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u32 candp1, candn;
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u32 best_delta = 0xffffffff;
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u32 target_frequency;
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u32 pixel_p1 = 1;
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u32 pixel_n = 1;
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u32 pixel_m1 = 1;
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u32 pixel_m2 = 1;
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u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000;
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u32 data_m1;
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u32 data_n1 = 0x00800000;
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u32 link_m1;
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u32 link_n1 = 0x00080000;
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write32(mmio + 0x00070080, 0x00000000);
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write32(mmio + DSPCNTR(0), 0x00000000);
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write32(mmio + 0x00071180, 0x00000000);
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write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);
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write32(mmio + 0x0007019c, 0x00000000);
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write32(mmio + 0x0007119c, 0x00000000);
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write32(mmio + 0x000ec008, 0x2c010000);
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write32(mmio + 0x000ec020, 0x2c010000);
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write32(mmio + 0x000ec038, 0x2c010000);
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write32(mmio + 0x000ec050, 0x2c010000);
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write32(mmio + 0x000ec408, 0x2c010000);
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write32(mmio + 0x000ec420, 0x2c010000);
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write32(mmio + 0x000ec438, 0x2c010000);
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write32(mmio + 0x000ec450, 0x2c010000);
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vga_gr_write(0x18, 0);
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write32(mmio + 0x00042004, 0x02000000);
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write32(mmio + 0x000fd034, 0x8421ffe0);
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/* Setup GTT. */
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for (i = 0; i < 0x2000; i++)
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{
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outl((i << 2) | 1, piobase);
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outl(physbase + (i << 12) + 1, piobase + 4);
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}
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vga_misc_write(0x67);
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const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
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0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
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0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
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0xff
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};
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vga_cr_write(0x11, 0);
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for (i = 0; i <= 0x18; i++)
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vga_cr_write(i, cr[i]);
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power_port(mmio);
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intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128);
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decode_edid(edid_data,
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sizeof(edid_data), &edid);
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/* Disable screen memory to prevent garbage from appearing. */
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vga_sr_write(1, vga_sr_read(1) | 0x20);
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hactive = edid.x_resolution;
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vactive = edid.y_resolution;
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right_border = edid.hborder;
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bottom_border = edid.vborder;
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hpolarity = (edid.phsync == '-');
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vpolarity = (edid.pvsync == '-');
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vsync = edid.vspw;
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hsync = edid.hspw;
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vblank = edid.vbl;
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hblank = edid.hbl;
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hfront_porch = edid.hso;
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vfront_porch = edid.vso;
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target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock
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: (2 * edid.pixel_clock);
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#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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vga_textmode_init();
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#else
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vga_sr_write(1, 1);
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vga_sr_write(0x2, 0xf);
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vga_sr_write(0x3, 0x0);
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vga_sr_write(0x4, 0xe);
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vga_gr_write(0, 0x0);
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vga_gr_write(1, 0x0);
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vga_gr_write(2, 0x0);
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vga_gr_write(3, 0x0);
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vga_gr_write(4, 0x0);
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vga_gr_write(5, 0x0);
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vga_gr_write(6, 0x5);
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vga_gr_write(7, 0xf);
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vga_gr_write(0x10, 0x1);
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vga_gr_write(0x11, 0);
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edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
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write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
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write32(mmio + DSPADDR(0), 0);
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write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
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write32(mmio + DSPSURF(0), 0);
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for (i = 0; i < 0x100; i++)
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write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
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#endif
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/* Find suitable divisors. */
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for (candp1 = 1; candp1 <= 8; candp1++) {
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for (candn = 5; candn <= 10; candn++) {
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u32 cur_frequency;
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u32 m; /* 77 - 131. */
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u32 denom; /* 35 - 560. */
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u32 current_delta;
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denom = candn * candp1 * 7;
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/* Doesnt overflow for up to
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5000000 kHz = 5 GHz. */
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m = (target_frequency * denom + 60000) / 120000;
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if (m < 77 || m > 131)
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continue;
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cur_frequency = (120000 * m) / denom;
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if (target_frequency > cur_frequency)
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current_delta = target_frequency - cur_frequency;
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else
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current_delta = cur_frequency - target_frequency;
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if (best_delta > current_delta) {
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best_delta = current_delta;
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pixel_n = candn;
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pixel_p1 = candp1;
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pixel_m2 = ((m + 3) % 5) + 7;
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pixel_m1 = (m - pixel_m2) / 5;
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}
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}
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}
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if (best_delta == 0xffffffff) {
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printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
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return 0;
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}
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link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
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data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
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/ (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4));
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printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
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hactive, vactive);
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printk(BIOS_DEBUG, "Borders %d x %d\n",
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right_border, bottom_border);
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printk(BIOS_DEBUG, "Blank %d x %d\n",
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hblank, vblank);
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printk(BIOS_DEBUG, "Sync %d x %d\n",
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hsync, vsync);
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printk(BIOS_DEBUG, "Front porch %d x %d\n",
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hfront_porch, vfront_porch);
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printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock
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? "Spread spectrum clock\n" : "DREF clock\n"));
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printk(BIOS_DEBUG,
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info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
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printk(BIOS_DEBUG, "Polarities %d, %d\n",
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hpolarity, vpolarity);
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printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
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data_m1, data_n1);
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printk(BIOS_DEBUG, "Link frequency %d kHz\n",
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link_frequency);
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printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",
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link_m1, link_n1);
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printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
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pixel_n, pixel_m1, pixel_m2, pixel_p1);
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printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
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120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
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/ (pixel_p1 * 7));
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write32(mmio + PCH_LVDS,
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(hpolarity << 20) | (vpolarity << 21)
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| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
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| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
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| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
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| LVDS_DETECTED);
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write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
|
||||
write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock
|
||||
? 0x1002 : 0x400));
|
||||
mdelay(1);
|
||||
write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
|
||||
| (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
|
||||
write32(mmio + _PCH_FP0(0),
|
||||
((pixel_n - 2) << 16)
|
||||
| ((pixel_m1 - 2) << 8) | pixel_m2);
|
||||
write32(mmio + PCH_DPLL_SEL, 8);
|
||||
write32(mmio + _PCH_DPLL(0),
|
||||
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
|
||||
| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
|
||||
: DPLLB_LVDS_P2_CLOCK_DIV_14)
|
||||
| (0x10000 << (pixel_p1 - 1))
|
||||
| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
|
||||
| (0x1 << (pixel_p1 - 1)));
|
||||
mdelay(1);
|
||||
write32(mmio + _PCH_DPLL(0),
|
||||
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
|
||||
| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
|
||||
: DPLLB_LVDS_P2_CLOCK_DIV_14)
|
||||
| (0x10000 << (pixel_p1 - 1))
|
||||
| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
|
||||
| (0x1 << (pixel_p1 - 1)));
|
||||
/* Re-lock the registers. */
|
||||
write32(mmio + PCH_PP_CONTROL,
|
||||
(read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
|
||||
|
||||
write32(mmio + PCH_LVDS,
|
||||
(hpolarity << 20) | (vpolarity << 21)
|
||||
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
|
||||
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
|
||||
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
|
||||
| LVDS_DETECTED);
|
||||
|
||||
write32(mmio + HTOTAL(0),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive - 1));
|
||||
write32(mmio + HBLANK(0),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive + right_border - 1));
|
||||
write32(mmio + HSYNC(0),
|
||||
((hactive + right_border + hfront_porch + hsync - 1) << 16)
|
||||
| (hactive + right_border + hfront_porch - 1));
|
||||
|
||||
write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive - 1));
|
||||
write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive + bottom_border - 1));
|
||||
write32(mmio + VSYNC(0),
|
||||
(vactive + bottom_border + vfront_porch + vsync - 1)
|
||||
| (vactive + bottom_border + vfront_porch - 1));
|
||||
|
||||
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
|
||||
|
||||
write32(mmio + PF_WIN_POS(0), 0);
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
|
||||
write32(mmio + PF_CTL(0),0);
|
||||
write32(mmio + PF_WIN_SZ(0), 0);
|
||||
#else
|
||||
write32(mmio + PIPESRC(0), (639 << 16) | 399);
|
||||
write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
|
||||
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
|
||||
#endif
|
||||
|
||||
mdelay(1);
|
||||
|
||||
write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
|
||||
write32(mmio + PIPE_DATA_N1(0), data_n1);
|
||||
write32(mmio + PIPE_LINK_M1(0), link_m1);
|
||||
write32(mmio + PIPE_LINK_N1(0), link_n1);
|
||||
|
||||
write32(mmio + 0x000f000c, 0x00002040);
|
||||
mdelay(1);
|
||||
write32(mmio + 0x000f000c, 0x00002050);
|
||||
write32(mmio + 0x00060100, 0x00044000);
|
||||
mdelay(1);
|
||||
write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
|
||||
write32(mmio + 0x000f000c, 0x00022050);
|
||||
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
|
||||
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
|
||||
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
|
||||
#else
|
||||
write32(mmio + CPU_VGACNTRL, 0x20298e);
|
||||
#endif
|
||||
train_link(mmio);
|
||||
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
|
||||
mdelay(1);
|
||||
#endif
|
||||
|
||||
write32(mmio + TRANS_HTOTAL(0),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive - 1));
|
||||
write32(mmio + TRANS_HBLANK(0),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive + right_border - 1));
|
||||
write32(mmio + TRANS_HSYNC(0),
|
||||
((hactive + right_border + hfront_porch + hsync - 1) << 16)
|
||||
| (hactive + right_border + hfront_porch - 1));
|
||||
|
||||
write32(mmio + TRANS_VTOTAL(0),
|
||||
((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive - 1));
|
||||
write32(mmio + TRANS_VBLANK(0),
|
||||
((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive + bottom_border - 1));
|
||||
write32(mmio + TRANS_VSYNC(0),
|
||||
(vactive + bottom_border + vfront_porch + vsync - 1)
|
||||
| (vactive + bottom_border + vfront_porch - 1));
|
||||
|
||||
write32(mmio + 0x00060100, 0xb01c4000);
|
||||
write32(mmio + 0x000f000c, 0x801a2350);
|
||||
mdelay(1);
|
||||
write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
| TRANS_STATE_MASK
|
||||
#endif
|
||||
);
|
||||
|
||||
write32(mmio + PCH_LVDS,
|
||||
LVDS_PORT_ENABLE
|
||||
| (hpolarity << 20) | (vpolarity << 21)
|
||||
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
|
||||
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
|
||||
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
|
||||
| LVDS_DETECTED);
|
||||
|
||||
write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
|
||||
write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
|
||||
mdelay(1);
|
||||
write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
|
||||
| PANEL_POWER_ON | PANEL_POWER_RESET);
|
||||
|
||||
printk (BIOS_DEBUG, "waiting for panel powerup\n");
|
||||
while (1) {
|
||||
u32 reg32;
|
||||
reg32 = read32(mmio + PCH_PP_STATUS);
|
||||
if (((reg32 >> 28) & 3) == 0)
|
||||
break;
|
||||
}
|
||||
printk (BIOS_DEBUG, "panel powered up\n");
|
||||
|
||||
write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
|
||||
|
||||
/* Enable screen memory. */
|
||||
vga_sr_write(1, vga_sr_read(1) & ~0x20);
|
||||
|
||||
/* Clear interrupts. */
|
||||
write32(mmio + DEIIR, 0xffffffff);
|
||||
write32(mmio + SDEIIR, 0xffffffff);
|
||||
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
|
||||
set_vbe_mode_info_valid(&edid, lfb);
|
||||
#endif
|
||||
|
||||
/* Linux relies on VBT for panel info. */
|
||||
optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START;
|
||||
optionrom_pcir_t *pcir;
|
||||
size_t vbt_size;
|
||||
size_t fake_oprom_size;
|
||||
struct device *dev;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(2, 0));
|
||||
|
||||
memset(oh, 0, 8192);
|
||||
|
||||
oh->signature = OPROM_SIGNATURE;
|
||||
oh->pcir_offset = 0x40;
|
||||
oh->vbt_offset = 0x80;
|
||||
|
||||
pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40);
|
||||
pcir->signature = 0x52494350; // PCIR
|
||||
pcir->vendor = dev->vendor;
|
||||
pcir->device = dev->device;
|
||||
pcir->length = sizeof(*pcir);
|
||||
pcir->revision = dev->class;
|
||||
pcir->classcode[0] = dev->class >> 8;
|
||||
pcir->classcode[1] = dev->class >> 16;
|
||||
pcir->classcode[2] = dev->class >> 24;
|
||||
pcir->indicator = 0x80;
|
||||
|
||||
vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80));
|
||||
fake_oprom_size = (0x80 + vbt_size + 511) / 512;
|
||||
oh->size = fake_oprom_size;
|
||||
pcir->imagelength = fake_oprom_size;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue