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AGESA fam15: Move LPC decode enable for serial port 

Move LPC decode enable out of agesawrapper.c. It should not be on the
execution path of AP CPUs and function is not related to AGESA per se.

Change-Id: I19c6a9c7d71c9899fdc898c09c337d747424fcec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7601
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Kyösti Mälkki 2014-11-21 17:40:37 +02:00
parent 27c4edace6
commit 9bb38c963f
2 changed files with 4 additions and 7 deletions
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7
src/mainboard/tyan/s8226/agesawrapper.c
View File

@ -176,8 +176,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@ -194,11 +192,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

4
src/mainboard/tyan/s8226/romstage.c
View File

@ -47,6 +47,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
post_code(0x31);
/* For serial port. */
device_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
/* Halt if there was a built in self test failure */
post_code(0x33);
report_bist_failure(bist);