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soc/intel/cannonlake: Configure voltage margining policies 

For systems that integrate GbE controllers, following parameters should be configured:
SlpS0WithGbeSupport: enable PchPmSlpS0VmRuntimeControl: disable,
PchPmSlpS0Vm070VSupport: disable, PchPmSlpS0Vm075VSupport: disable.

TEST=boot on any GbE supported WHL platform

Change-Id: I02aaf0b77b8fc1555a3a424c02acfada21707d0e
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Krzysztof Sywula 2019-03-21 17:11:02 -07:00 committed by Patrick Georgi
parent 7458629de3
commit 9bc9da9d7e
2 changed files with 17 additions and 1 deletions
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9
src/soc/intel/cannonlake/chip.h
View File

@ -138,6 +138,15 @@ struct soc_intel_cannonlake_config {
uint8_t SataPortsEnable[8];
uint8_t SataPortsDevSlp[8];
/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
uint8_t SlpS0WithGbeSupport;
/* SLP_S0 Voltage Margining Policy. 0: disable, 1: enable */
uint8_t PchPmSlpS0VmRuntimeControl;
/* SLP_S0 Voltage Margining 0.70V Policy. 0: disable, 1: enable */
uint8_t PchPmSlpS0Vm070VSupport;
/* SLP_S0 Voltage Margining 0.75V Policy. 0: disable, 1: enable */
uint8_t PchPmSlpS0Vm075VSupport;
/* Audio related */
uint8_t PchHdaDspEnable;

9
src/soc/intel/cannonlake/fsp_params.c
View File

@ -161,8 +161,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev = dev_find_slot(0, PCH_DEVFN_GBE);
if (!dev)
params->PchLanEnable = 0;
else
else {
params->PchLanEnable = dev->enabled;
if (config->s0ix_enable) {
params->SlpS0WithGbeSupport = 1;
params->PchPmSlpS0VmRuntimeControl = 0;
params->PchPmSlpS0Vm070VSupport = 0;
params->PchPmSlpS0Vm075VSupport = 0;
}
}
/* Audio */
params->PchHdaDspEnable = config->PchHdaDspEnable;