Unify DIMM SPD addressing. For Geode, change the

addressing scheme to match the rest of the tree
(0x50 instead of 0xa0).

abuild tested.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-11-20 10:31:00 +00:00 committed by Patrick Georgi
parent 622824cadb
commit 9bd9a90d6a
47 changed files with 54 additions and 191 deletions

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@ -156,5 +156,15 @@
#define MODULE_BUFFERED 1 #define MODULE_BUFFERED 1
#define MODULE_REGISTERED 2 #define MODULE_REGISTERED 2
/* DIMM SPD addresses */
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
#endif /* _SPD_H_ */ #endif /* _SPD_H_ */

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@ -30,6 +30,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -45,8 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#define ManualConf 0 /* Do automatic strapped PLL config */ #define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ #define PLLMSRhi 0x000005DD /* Manual settings for the PLL */
#define PLLMSRlo 0x00DE60EE #define PLLMSRlo 0x00DE60EE
#define DIMM0 0xA0
#define DIMM1 0xA2
#include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/pll_reset.c"

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@ -20,9 +20,6 @@
#define RC0 (6<<8) #define RC0 (6<<8)
#define RC1 (7<<8) #define RC1 (7<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define SMBUS_HUB 0x71 #define SMBUS_HUB 0x71
#include <stdint.h> #include <stdint.h>
@ -43,6 +40,7 @@
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/it8712f_early_serial.c" #include "superio/ite/it8712f/it8712f_early_serial.c"
#include <spd.h>
#include <usbdebug.h> #include <usbdebug.h>

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@ -20,9 +20,6 @@
#define RC0 (6<<8) #define RC0 (6<<8)
#define RC1 (7<<8) #define RC1 (7<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define SMBUS_HUB 0x71 #define SMBUS_HUB 0x71
#include <stdint.h> #include <stdint.h>
@ -34,6 +31,7 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"

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@ -57,6 +57,7 @@ static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/rs780/rs780_early_setup.c" #include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c" #include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
static void activate_spd_rom(const struct mem_controller *ctrl) static void activate_spd_rom(const struct mem_controller *ctrl)
{ {
@ -90,11 +91,6 @@ static int spd_read_byte(u32 device, u32 address)
#define RC00 0 #define RC00 0
#define RC01 1 #define RC01 1
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

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@ -30,6 +30,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@ -42,8 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#define ManualConf 0 /* Do automatic strapped PLL config */ #define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ #define PLLMSRhi 0x00001490 /* manual settings for the PLL */
#define PLLMSRlo 0x02000030 #define PLLMSRlo 0x02000030
#define DIMM0 0xA0
#define DIMM1 0xA2
#include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/pll_reset.c"

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@ -17,9 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#define DIMM0 0x50
#define DIMM1 0x51
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -39,6 +36,7 @@
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/it8712f_early_serial.c" #include "superio/ite/it8712f/it8712f_early_serial.c"
#include <usbdebug.h> #include <usbdebug.h>
#include <spd.h>
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"

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@ -9,15 +9,13 @@
#include "cpu/x86/msr.h" #include "cpu/x86/msr.h"
#include <cpu/amd/gx2def.h> #include <cpu/amd/gx2def.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c"
#define DIMM0 0xA0
#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
static inline int spd_read_byte(unsigned device, unsigned address) static inline int spd_read_byte(unsigned device, unsigned address)
{ {
if (device != DIMM0) if (device != DIMM0)

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@ -92,22 +92,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "resourcemap.c" #include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#define RC0 ((1<<0)<<8) #define RC0 ((1<<0)<<8)
#define RC1 ((1<<1)<<8) #define RC1 ((1<<1)<<8)
#define RC2 ((1<<2)<<8) #define RC2 ((1<<2)<<8)
#define RC3 ((1<<3)<<8) #define RC3 ((1<<3)<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"

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@ -84,17 +84,13 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c" #include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
//#include "spd_addr.h" //#include "spd_addr.h"
#define RC00 0 #define RC00 0
#define RC01 1 #define RC01 1
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

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@ -32,13 +32,11 @@
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include "spd_table.h" #include "spd_table.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c"
#define DIMM0 0xA0
#define DIMM1 0xA2
static int spd_read_byte(unsigned device, unsigned address) static int spd_read_byte(unsigned device, unsigned address)
{ {
int i; int i;

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@ -21,9 +21,6 @@
#define RC0 (6<<8) #define RC0 (6<<8)
#define RC1 (7<<8) #define RC1 (7<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define SMBUS_HUB 0x71 #define SMBUS_HUB 0x71
#include <stdint.h> #include <stdint.h>
@ -40,6 +37,7 @@
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c" #include "lib/delay.c"
#include <spd.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"

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@ -84,17 +84,13 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c" #include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
//#include "spd_addr.h" //#include "spd_addr.h"
#define RC00 0 #define RC00 0
#define RC01 1 #define RC01 1
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

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@ -70,16 +70,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "resourcemap.c" #include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#define RC0 (6<<8) #define RC0 (6<<8)
#define RC1 (7<<8) #define RC1 (7<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"

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@ -11,6 +11,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -26,8 +27,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define ManualConf 0 /* Do automatic strapped PLL config */ #define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ #define PLLMSRhi 0x00001490 /* manual settings for the PLL */
#define PLLMSRlo 0x02000030 #define PLLMSRlo 0x02000030
#define DIMM0 0xA0
#define DIMM1 0xA2
#include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c" #include "northbridge/amd/lx/raminit.c"

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@ -80,16 +80,12 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c" #include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
#define RC00 0 #define RC00 0
#define RC01 1 #define RC01 1
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

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@ -84,16 +84,12 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c" #include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
#define RC00 0 #define RC00 0
#define RC01 1 #define RC01 1
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

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@ -92,15 +92,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "lib/generic_sdram.c" #include "lib/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#define RC0 ((1<<1)<<8) // Not sure about these values #define RC0 ((1<<1)<<8) // Not sure about these values
#define RC1 ((1<<2)<<8) // Not sure about these values #define RC1 ((1<<2)<<8) // Not sure about these values
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"

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@ -92,22 +92,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c" #include "lib/generic_sdram.c"
#include <spd.h>
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
//first node
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
//second node
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"

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@ -87,17 +87,13 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c" #include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
//#include "spd_addr.h" //#include "spd_addr.h"
#define RC00 0 #define RC00 0
#define RC01 1 #define RC01 1
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

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@ -30,6 +30,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -50,9 +51,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
/* Hold Count - how long we will sit in reset */ /* Hold Count - how long we will sit in reset */
#define PLLMSRlo 0x00DE6000 #define PLLMSRlo 0x00DE6000
#define DIMM0 0xA0
#define DIMM1 0xA2
#include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c" #include "northbridge/amd/lx/raminit.c"

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@ -37,7 +37,7 @@
#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/mtrr/earlymtrr.c"
#include "superio/intel/i3100/i3100_early_serial.c" #include "superio/intel/i3100/i3100_early_serial.c"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "spd.h" #include <spd.h>
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0) #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)

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@ -81,15 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "resourcemap.c" #include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"

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@ -81,15 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"

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@ -81,15 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"

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@ -92,17 +92,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c" #include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c" #include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
#define RC00 0 #define RC00 0
#define RC01 1 #define RC01 1
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {

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@ -21,9 +21,6 @@
#define RC0 (6<<8) #define RC0 (6<<8)
#define RC1 (7<<8) #define RC1 (7<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define SMBUS_HUB 0x71 #define SMBUS_HUB 0x71
#include <stdint.h> #include <stdint.h>
@ -40,6 +37,7 @@
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c" #include "lib/delay.c"
#include <spd.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"

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@ -11,15 +11,13 @@
#include <cpu/amd/gx2def.h> #include <cpu/amd/gx2def.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5535/cs5535.h" #include "southbridge/amd/cs5535/cs5535.h"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "southbridge/amd/cs5535/cs5535_early_smbus.c" #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
#include "southbridge/amd/cs5535/cs5535_early_setup.c" #include "southbridge/amd/cs5535/cs5535_early_setup.c"
#define DIMM0 0xA0
#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */ static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */
0xFF, 0xFF, /* only values used by raminit.c are set */ 0xFF, 0xFF, /* only values used by raminit.c are set */
[SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */ [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */

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@ -33,6 +33,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@ -44,8 +45,6 @@
#define ManualConf 1 /* No automatic strapped PLL config */ #define ManualConf 1 /* No automatic strapped PLL config */
#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ #define PLLMSRhi 0x0000049C /* Manual settings for the PLL */
#define PLLMSRlo 0x00DE6001 #define PLLMSRlo 0x00DE6001
#define DIMM0 0xA0
#define DIMM1 0xA2
static inline int spd_read_byte(unsigned int device, unsigned int address) static inline int spd_read_byte(unsigned int device, unsigned int address)
{ {

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@ -34,6 +34,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@ -49,8 +50,6 @@
#define ManualConf 1 /* No automatic strapped PLL config */ #define ManualConf 1 /* No automatic strapped PLL config */
#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ #define PLLMSRhi 0x0000059C /* Manual settings for the PLL */
#define PLLMSRlo 0x00DE6001 #define PLLMSRlo 0x00DE6001
#define DIMM0 0xA0
#define DIMM1 0xA2
static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I
0xFF, 0xFF, // only values used by Geode-LX raminit.c are set 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set

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@ -33,6 +33,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@ -41,8 +42,6 @@
#define ManualConf 1 /* No automatic strapped PLL config */ #define ManualConf 1 /* No automatic strapped PLL config */
#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ #define PLLMSRhi 0x0000049C /* Manual settings for the PLL */
#define PLLMSRlo 0x00DE6001 #define PLLMSRlo 0x00DE6001
#define DIMM0 0xA0
#define DIMM1 0xA2
static inline int spd_read_byte(unsigned int device, unsigned int address) static inline int spd_read_byte(unsigned int device, unsigned int address)
{ {

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@ -34,6 +34,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@ -49,8 +50,6 @@
#define ManualConf 1 /* No automatic strapped PLL config */ #define ManualConf 1 /* No automatic strapped PLL config */
#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ #define PLLMSRhi 0x0000059C /* Manual settings for the PLL */
#define PLLMSRlo 0x00DE6001 #define PLLMSRlo 0x00DE6001
#define DIMM0 0xA0
#define DIMM1 0xA2
static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I
0xFF, 0xFF, // only values used by Geode-LX raminit.c are set 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set

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@ -93,19 +93,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "resourcemap.c" #include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#define RC0 (0x10<<8) #define RC0 (0x10<<8)
#define RC1 (0x01<<8) #define RC1 (0x01<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"

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@ -32,6 +32,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -106,9 +107,6 @@ static u8 spd_read_byte(u8 device, u8 address)
#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
#define PLLMSRlo 0x02000030 #define PLLMSRlo 0x02000030
#define DIMM0 0xa0
#define DIMM1 0xa2
#include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c" #include "northbridge/amd/lx/raminit.c"

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@ -32,6 +32,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -105,9 +106,6 @@ static u8 spd_read_byte(u8 device, u8 address)
#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
#define PLLMSRlo 0x02000030 #define PLLMSRlo 0x02000030
#define DIMM0 0xa0
#define DIMM1 0xa2
#include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c" #include "northbridge/amd/lx/raminit.c"

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@ -20,9 +20,6 @@
#define RC0 (6<<8) #define RC0 (6<<8)
#define RC1 (7<<8) #define RC1 (7<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define SMBUS_HUB 0x71 #define SMBUS_HUB 0x71
#include <stdint.h> #include <stdint.h>
@ -39,6 +36,7 @@
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c" #include "lib/delay.c"
#include <spd.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"

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@ -20,9 +20,6 @@
#define RC0 (6<<8) #define RC0 (6<<8)
#define RC1 (7<<8) #define RC1 (7<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define SMBUS_HUB 0x71 #define SMBUS_HUB 0x71
#include <stdint.h> #include <stdint.h>
@ -39,6 +36,7 @@
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c" #include "lib/delay.c"
#include <spd.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"

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@ -31,6 +31,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@ -43,8 +44,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#define ManualConf 1 /* Do automatic strapped PLL config */ #define ManualConf 1 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x0000059C /* manual settings for the PLL */ #define PLLMSRhi 0x0000059C /* manual settings for the PLL */
#define PLLMSRlo 0x00DE602E #define PLLMSRlo 0x00DE602E
#define DIMM0 0xA0
#define DIMM1 0xA2
#include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/pll_reset.c"

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@ -84,19 +84,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "resourcemap.c" #include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#define RC0 ((1<<2)<<8) #define RC0 ((1<<2)<<8)
#define RC1 ((1<<1)<<8) #define RC1 ((1<<1)<<8)
#define RC2 ((1<<4)<<8) #define RC2 ((1<<4)<<8)
#define RC3 ((1<<3)<<8) #define RC3 ((1<<3)<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"

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@ -92,19 +92,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "resourcemap.c" #include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#define RC0 ((1<<2)<<8) #define RC0 ((1<<2)<<8)
#define RC1 ((1<<1)<<8) #define RC1 ((1<<1)<<8)
#define RC2 ((1<<4)<<8) #define RC2 ((1<<4)<<8)
#define RC3 ((1<<3)<<8) #define RC3 ((1<<3)<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"

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@ -32,6 +32,7 @@
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -47,8 +48,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#define ManualConf 0 /* Do automatic strapped PLL config */ #define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
#define PLLMSRlo 0x02000030 #define PLLMSRlo 0x02000030
#define DIMM0 0xA0
#define DIMM1 0xA2
#include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/pll_reset.c"

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@ -30,13 +30,11 @@
#include "cpu/x86/msr.h" #include "cpu/x86/msr.h"
#include <cpu/amd/gx2def.h> #include <cpu/amd/gx2def.h>
#include <cpu/amd/geode_post_code.h> #include <cpu/amd/geode_post_code.h>
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c"
#define DIMM0 0xA0
#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
static inline int spd_read_byte(unsigned int device, unsigned int address) static inline int spd_read_byte(unsigned int device, unsigned int address)
{ {
if (device != DIMM0) if (device != DIMM0)

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@ -37,7 +37,6 @@
/* Define register settings */ /* Define register settings */
#define HOST_RESET 0xff #define HOST_RESET 0xff
#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus
#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
#define SMBUS_TIMEOUT (100*1000*10) #define SMBUS_TIMEOUT (100*1000*10)

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@ -40,7 +40,6 @@
/* Define register settings */ /* Define register settings */
#define HOST_RESET 0xff #define HOST_RESET 0xff
#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus
#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
#define SMBUS_TIMEOUT (100*1000*10) #define SMBUS_TIMEOUT (100*1000*10)
@ -121,9 +120,7 @@ static unsigned int get_spd_data(unsigned int dimm, unsigned int offset)
smbus_wait_until_ready(); smbus_wait_until_ready();
/* Do some mathmatic magic */ /* Do some mathmatic magic */
dimm = (dimm << 1); dimm = (DIMM0 + dimm) << 1;
dimm &= 0x0E;
dimm |= 0xA0;
outb(dimm | 0x1, SMBXMITADD); outb(dimm | 0x1, SMBXMITADD);
outb(offset, SMBHSTCMD); outb(offset, SMBHSTCMD);

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@ -165,7 +165,7 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
goto err; goto err;
} }
if ((smbus_send_slave_address(smbus_io_base, device))) { if ((smbus_send_slave_address(smbus_io_base, device << 1))) {
error = 3; error = 3;
goto err; goto err;
} }
@ -182,7 +182,7 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
goto err; goto err;
} }
if ((smbus_send_slave_address(smbus_io_base, device | 0x01))) { if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) {
error = 6; error = 6;
goto err; goto err;
} }

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@ -16,7 +16,6 @@
/* Define register settings */ /* Define register settings */
#define HOST_RESET 0xff #define HOST_RESET 0xff
#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus
#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ

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@ -16,7 +16,6 @@
/* Define register settings */ /* Define register settings */
#define HOST_RESET 0xff #define HOST_RESET 0xff
#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus
#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ