soc/intel/cannonlake: SATA and DMI power optimize

Expose the FSP interface to enable SATA and PCH side DMI power optimize
options. Actual step executed in FSP, step defined in cannonlake pch
BIOS spec(CDI# 570374).

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78
Reviewed-on: https://review.coreboot.org/c/30211
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/chip.h

@@ -296,6 +296,12 @@ struct soc_intel_cannonlake_config {
 	uint8_t SlowSlewRateForGt;
 	uint8_t SlowSlewRateForSa;
 	uint8_t SlowSlewRateForFivr;
+
+	/* DMI Power Optimizer */
+	uint8_t dmipwroptimize;
+
+	/* SATA Power Optimizer */
+	uint8_t satapwroptimize;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;

src/soc/intel/cannonlake/fsp_params.c

@@ -221,6 +221,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;
 	params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
 	params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
+
+	/* Power Optimizer */
+	params->PchPwrOptEnable = config->dmipwroptimize;
+	params->SataPwrOptEnable = config->satapwroptimize;
 }
 
 /* Mainboard GPIO Configuration */