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mainboard/google/hatch/puff: Toggle on TetonGlacierMode 

Leverage in Puff to avoid diskswap variants. Later this could become
part of the baseboard definition and hatch diskswap variants migrated
over to use it as well.

BUG=b:149171631
BRANCH=none
TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and
run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration
on Puff.

Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Edward O'Callaghan 2020-02-21 16:15:26 +11:00 committed by Edward O'Callaghan
parent fa043c4e9d
commit 9bffbc0873
1 changed files with 7 additions and 0 deletions
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7
src/mainboard/google/hatch/variants/puff/overridetree.cb
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@ -2,6 +2,9 @@ chip soc/intel/cannonlake
# Enable heci communication
register "HeciEnabled" = "1"
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
@ -166,6 +169,9 @@ chip soc/intel/cannonlake
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"
@ -281,6 +287,7 @@ chip soc/intel/cannonlake
end
end # FSP requires func0 be enabled.
device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1).
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
device pci 1e.3 off end # GSPI #1
end