GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/poppy/variants/nautilus: Enable AER and LTR for root port 1 

Similar to other KBL projects, this change enables AER and LTR for
root port 1 on poppy.

BUG=b:65570878

Change-Id: Iadad3d2fc46cbba575a776071305925c529a6760
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-12-17 20:31:18 -08:00
parent f7cd2eb55d
commit 9c12e90819
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -157,6 +157,10 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqSupport[0]" = "1"
# RP 1 uses SRCCLKREQ1# # RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkReqNumber[0]" = "1"
# RP 1, Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[0]" = "1"
# RP 1, Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port