soc/intel/skylake: Enable thermal subsystem depending on devicetree
Currently SA thermal subsystem gets enabled by the option Device4Enable, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the SA thermal subsystem controller. All corresponding mainboards were checked if the devicetree configuration matches the Device4Enable setting, and missing entries were added. Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
c787a246f9
commit
9c1c00968c
|
@ -54,7 +54,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "1"
|
register "HeciEnabled" = "1"
|
||||||
register "SaGv" = "SaGv_Enabled"
|
register "SaGv" = "SaGv_Enabled"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -123,6 +122,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 off end # USB xDCI (OTG)
|
device pci 14.1 off end # USB xDCI (OTG)
|
||||||
device pci 14.2 on end # Thermal Subsystem
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
|
|
@ -38,7 +38,6 @@ chip soc/intel/skylake
|
||||||
# FSP Configuration
|
# FSP Configuration
|
||||||
register "ScsEmmcHs400Enabled" = "1"
|
register "ScsEmmcHs400Enabled" = "1"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "SaGv" = "SaGv_Enabled"
|
register "SaGv" = "SaGv_Enabled"
|
||||||
register "SaImguEnable" = "0"
|
register "SaImguEnable" = "0"
|
||||||
register "Cio2Enable" = "0"
|
register "Cio2Enable" = "0"
|
||||||
|
|
|
@ -47,7 +47,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "3"
|
register "SaGv" = "3"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -247,6 +246,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on
|
device pci 14.0 on
|
||||||
chip drivers/usb/acpi
|
chip drivers/usb/acpi
|
||||||
register "desc" = ""Root Hub""
|
register "desc" = ""Root Hub""
|
||||||
|
|
|
@ -78,7 +78,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "2"
|
register "ScsSdCardEnabled" = "2"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "3"
|
register "SaGv" = "3"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -322,6 +321,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on
|
device pci 14.0 on
|
||||||
chip drivers/usb/acpi
|
chip drivers/usb/acpi
|
||||||
register "desc" = ""Root Hub""
|
register "desc" = ""Root Hub""
|
||||||
|
|
|
@ -49,7 +49,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "3"
|
register "SaGv" = "3"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -102,6 +101,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 off end # USB xDCI (OTG)
|
device pci 14.1 off end # USB xDCI (OTG)
|
||||||
device pci 14.2 on end # Thermal Subsystem
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
|
|
@ -54,7 +54,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "3"
|
register "SaGv" = "3"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -248,6 +247,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 13.0 off end # Integrated Sensor Hub
|
device pci 13.0 off end # Integrated Sensor Hub
|
||||||
device pci 14.0 on
|
device pci 14.0 on
|
||||||
chip drivers/usb/acpi
|
chip drivers/usb/acpi
|
||||||
|
|
|
@ -44,7 +44,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "2"
|
register "ScsSdCardEnabled" = "2"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "3"
|
register "SaGv" = "3"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -268,6 +267,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 on end # USB xDCI (OTG)
|
device pci 14.1 on end # USB xDCI (OTG)
|
||||||
device pci 14.2 on end # Thermal Subsystem
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
|
|
@ -43,7 +43,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "3"
|
register "SaGv" = "3"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -283,6 +282,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 on end # USB xDCI (OTG)
|
device pci 14.1 on end # USB xDCI (OTG)
|
||||||
device pci 14.2 on end # Thermal Subsystem
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
|
|
@ -44,7 +44,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "2"
|
register "ScsSdCardEnabled" = "2"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "3"
|
register "SaGv" = "3"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -289,6 +288,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 on end # USB xDCI (OTG)
|
device pci 14.1 on end # USB xDCI (OTG)
|
||||||
device pci 14.2 on end # Thermal Subsystem
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
|
|
@ -49,7 +49,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "3"
|
register "SaGv" = "3"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -268,7 +267,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on
|
device pci 14.0 on
|
||||||
chip drivers/usb/acpi
|
chip drivers/usb/acpi
|
||||||
register "desc" = ""Root Hub""
|
register "desc" = ""Root Hub""
|
||||||
|
|
|
@ -54,7 +54,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "2"
|
register "ScsSdCardEnabled" = "2"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "3"
|
register "SaGv" = "3"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -247,6 +246,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on
|
device pci 14.0 on
|
||||||
chip drivers/usb/acpi
|
chip drivers/usb/acpi
|
||||||
register "desc" = ""Root Hub""
|
register "desc" = ""Root Hub""
|
||||||
|
|
|
@ -44,7 +44,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "2"
|
register "ScsSdCardEnabled" = "2"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "3"
|
register "SaGv" = "3"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -269,6 +268,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 on end # USB xDCI (OTG)
|
device pci 14.1 on end # USB xDCI (OTG)
|
||||||
device pci 14.2 on end # Thermal Subsystem
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
|
|
@ -28,7 +28,6 @@ chip soc/intel/skylake
|
||||||
register "ScsEmmcHs400Enabled" = "1"
|
register "ScsEmmcHs400Enabled" = "1"
|
||||||
register "ScsSdCardEnabled" = "2"
|
register "ScsSdCardEnabled" = "2"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "SaGv" = "SaGv_Enabled"
|
register "SaGv" = "SaGv_Enabled"
|
||||||
register "PchHdaVcType" = "Vc1"
|
register "PchHdaVcType" = "Vc1"
|
||||||
|
|
||||||
|
@ -121,6 +120,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 off end # USB xDCI (OTG)
|
device pci 14.1 off end # USB xDCI (OTG)
|
||||||
device pci 14.2 on end # Thermal Subsystem
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
|
|
@ -4,7 +4,6 @@ chip soc/intel/skylake
|
||||||
register "DspEnable" = "0"
|
register "DspEnable" = "0"
|
||||||
register "ScsEmmcHs400Enabled" = "0"
|
register "ScsEmmcHs400Enabled" = "0"
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "Device4Enable" = "0"
|
|
||||||
register "PmTimerDisabled" = "0"
|
register "PmTimerDisabled" = "0"
|
||||||
|
|
||||||
register "serirq_mode" = "SERIRQ_CONTINUOUS"
|
register "serirq_mode" = "SERIRQ_CONTINUOUS"
|
||||||
|
@ -117,6 +116,7 @@ chip soc/intel/skylake
|
||||||
}"
|
}"
|
||||||
|
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
|
device pci 04.0 off end # SA thermal subsystem
|
||||||
device pci 17.0 on end # SATA
|
device pci 17.0 on end # SATA
|
||||||
device pci 19.1 on end # I2C #5
|
device pci 19.1 on end # I2C #5
|
||||||
device pci 1e.1 on end # UART #1
|
device pci 1e.1 on end # UART #1
|
||||||
|
|
|
@ -29,7 +29,6 @@ chip soc/intel/skylake
|
||||||
register "ScsEmmcHs400Enabled" = "1"
|
register "ScsEmmcHs400Enabled" = "1"
|
||||||
register "ScsSdCardEnabled" = "2"
|
register "ScsSdCardEnabled" = "2"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "SaGv_Enabled"
|
register "SaGv" = "SaGv_Enabled"
|
||||||
register "PmTimerDisabled" = "1"
|
register "PmTimerDisabled" = "1"
|
||||||
|
@ -175,6 +174,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 off end # USB xDCI (OTG)
|
device pci 14.1 off end # USB xDCI (OTG)
|
||||||
device pci 14.2 on end # Thermal Subsystem
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
|
|
@ -23,7 +23,6 @@ chip soc/intel/skylake
|
||||||
register "ScsEmmcHs400Enabled" = "0"
|
register "ScsEmmcHs400Enabled" = "0"
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "0"
|
|
||||||
|
|
||||||
register "SaGv" = "SaGv_Enabled"
|
register "SaGv" = "SaGv_Enabled"
|
||||||
register "PmTimerDisabled" = "0"
|
register "PmTimerDisabled" = "0"
|
||||||
|
@ -211,6 +210,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 off end # SA thermal subsystem
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 off end # USB xDCI (OTG)
|
device pci 14.1 off end # USB xDCI (OTG)
|
||||||
device pci 14.2 on end # Thermal Subsystem
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
|
|
@ -54,7 +54,6 @@ chip soc/intel/skylake
|
||||||
register "ScsEmmcHs400Enabled" = "0"
|
register "ScsEmmcHs400Enabled" = "0"
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "1"
|
register "HeciEnabled" = "1"
|
||||||
register "SaGv" = "SaGv_Enabled"
|
register "SaGv" = "SaGv_Enabled"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -174,6 +173,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 on end # USB xDCI (OTG)
|
device pci 14.1 on end # USB xDCI (OTG)
|
||||||
device pci 14.2 on end # Thermal Subsystem
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
|
|
@ -43,7 +43,6 @@ chip soc/intel/skylake
|
||||||
register "ScsEmmcHs400Enabled" = "0"
|
register "ScsEmmcHs400Enabled" = "0"
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "0"
|
|
||||||
register "HeciEnabled" = "1"
|
register "HeciEnabled" = "1"
|
||||||
register "PmTimerDisabled" = "1"
|
register "PmTimerDisabled" = "1"
|
||||||
register "SaGv" = "SaGv_Enabled"
|
register "SaGv" = "SaGv_Enabled"
|
||||||
|
@ -219,6 +218,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 off end # SA thermal subsystem
|
||||||
device pci 08.0 off end # Gaussian Mixture Model
|
device pci 08.0 off end # Gaussian Mixture Model
|
||||||
device pci 13.0 off end # Integrated Sensor Hub
|
device pci 13.0 off end # Integrated Sensor Hub
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
|
|
|
@ -60,7 +60,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "0"
|
register "HeciEnabled" = "0"
|
||||||
register "SaGv" = "3"
|
register "SaGv" = "3"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -171,6 +170,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 04.0 on end # SA thermal subsystem
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 on end # USB xDCI (OTG)
|
device pci 14.1 on end # USB xDCI (OTG)
|
||||||
device pci 14.2 on end # Thermal Subsystem
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
|
|
@ -40,7 +40,6 @@ chip soc/intel/skylake
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "PttSwitch" = "0"
|
register "PttSwitch" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "HeciEnabled" = "1"
|
register "HeciEnabled" = "1"
|
||||||
register "SaGv" = "SaGv_Enabled"
|
register "SaGv" = "SaGv_Enabled"
|
||||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||||
|
@ -189,7 +188,7 @@ chip soc/intel/skylake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
device pci 00.0 on end # Host Bridge
|
device pci 00.0 on end # Host Bridge
|
||||||
device pci 02.0 on end # Integrated Graphics Device
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
device pci 04.0 off end # Thermal Subsystem
|
device pci 04.0 on end # Thermal Subsystem
|
||||||
device pci 08.0 off end # Gaussian Mixture Model
|
device pci 08.0 off end # Gaussian Mixture Model
|
||||||
device pci 14.0 on end # USB xHCI
|
device pci 14.0 on end # USB xHCI
|
||||||
device pci 14.1 off end # USB xDCI (OTG)
|
device pci 14.1 off end # USB xDCI (OTG)
|
||||||
|
|
|
@ -10,7 +10,6 @@ chip soc/intel/skylake
|
||||||
register "ScsEmmcHs400Enabled" = "0"
|
register "ScsEmmcHs400Enabled" = "0"
|
||||||
register "ScsSdCardEnabled" = "0"
|
register "ScsSdCardEnabled" = "0"
|
||||||
register "SkipExtGfxScan" = "1"
|
register "SkipExtGfxScan" = "1"
|
||||||
register "Device4Enable" = "1"
|
|
||||||
register "SaGv" = "SaGv_Disabled"
|
register "SaGv" = "SaGv_Disabled"
|
||||||
|
|
||||||
# SATA configuration
|
# SATA configuration
|
||||||
|
|
|
@ -278,7 +278,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
|
||||||
params->PchHdaVcType = config->PchHdaVcType;
|
params->PchHdaVcType = config->PchHdaVcType;
|
||||||
params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
|
params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
|
||||||
params->PchHdaDspEnable = config->DspEnable;
|
params->PchHdaDspEnable = config->DspEnable;
|
||||||
params->Device4Enable = config->Device4Enable;
|
|
||||||
|
dev = pcidev_path_on_root(SA_DEVFN_TS);
|
||||||
|
params->Device4Enable = dev && dev->enabled;
|
||||||
params->EnableTcoTimer = !config->PmTimerDisabled;
|
params->EnableTcoTimer = !config->PmTimerDisabled;
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -336,7 +336,6 @@ struct soc_intel_skylake_config {
|
||||||
u32 LogoPtr;
|
u32 LogoPtr;
|
||||||
u32 LogoSize;
|
u32 LogoSize;
|
||||||
u32 GraphicsConfigPtr;
|
u32 GraphicsConfigPtr;
|
||||||
u8 Device4Enable;
|
|
||||||
u8 RtcLock;
|
u8 RtcLock;
|
||||||
/* GPIO IRQ Route The valid values is 14 or 15*/
|
/* GPIO IRQ Route The valid values is 14 or 15*/
|
||||||
u8 GpioIrqSelect;
|
u8 GpioIrqSelect;
|
||||||
|
|
Loading…
Reference in New Issue