Add SDRAMPWR_4DIMM Kconfig option (not user-visible in menuconfig).

Each Intel 440BX board should select this option if it has 4 DIMM
slots on the PCB, and _not_ select it (it defaults to 'n') if it
has 3 DIMMs on the PCB.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/asus/p2b-d/Kconfig

@@ -31,6 +31,7 @@ config BOARD_ASUS_P2B_D
 	select SMP
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256
+	select SDRAMPWR_4DIMM
 
 config MAINBOARD_DIR
 	string

src/mainboard/asus/p2b-ds/Kconfig

@@ -31,6 +31,7 @@ config BOARD_ASUS_P2B_DS
 	select SMP
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256
+	select SDRAMPWR_4DIMM
 
 config MAINBOARD_DIR
 	string

src/mainboard/asus/p2b-ls/Kconfig

@@ -29,6 +29,7 @@ config BOARD_ASUS_P2B_LS
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256
+	select SDRAMPWR_4DIMM
 
 config MAINBOARD_DIR
 	string

src/mainboard/asus/p3b-f/Kconfig

@@ -29,6 +29,7 @@ config BOARD_ASUS_P3B_F
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_256
+	select SDRAMPWR_4DIMM
 
 config MAINBOARD_DIR
 	string

src/northbridge/intel/i440bx/Kconfig

@@ -22,3 +22,16 @@ config NORTHBRIDGE_INTEL_I440BX
 	bool
 	select HAVE_HIGH_TABLES
 
+config SDRAMPWR_4DIMM
+	bool
+	depends on NORTHBRIDGE_INTEL_I440BX
+	default n
+	help
+	  This option affects how the SDRAMC register is programmed.
+	  Memory clock signals will not be routed properly if this option
+	  is set wrong.
+	
+	  If your board has 4 DIMM slots, you must use select this option, in
+	  your Kconfig file of the board. On boards with 3 DIMM slots,
+	  do _not_ select this option.
+

src/northbridge/intel/i440bx/raminit.c

@@ -292,7 +292,11 @@ static const long register_values[] = {
 	 *         0 = 3 clocks of RAS# precharge
 	 *         1 = 2 clocks of RAS# precharge
 	 */
-	SDRAMC + 0, 0x00, 0x00,
+#if CONFIG_SDRAMPWR_4DIMM
+	SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */
+#else
+	SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots.*/
+#endif
 	SDRAMC + 1, 0x00, 0x00,
 
 	/* PGPOL - Paging Policy Register