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soc/intel/braswell: Hide some Kconfig options in menuconfig 

Don't allow the user to set PCIe configspace base address.

Don't allow the user to set the DCACHE size and base.

Change-Id: I7a42cc5f6098214364624bcfa3cbd93b4903ee84
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Arthur Heymans 2017-06-13 14:47:28 +02:00 committed by Martin Roth
parent 432ac615d0
commit 9c27eda052
1 changed files with 3 additions and 3 deletions
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6
src/soc/intel/braswell/Kconfig
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@ -55,7 +55,7 @@ config BOOTBLOCK_CPU_INIT
default "soc/intel/braswell/bootblock/bootblock.c" default "soc/intel/braswell/bootblock/bootblock.c"
config MMCONF_BASE_ADDRESS config MMCONF_BASE_ADDRESS
hex "PCIe CFG Base Address" hex
default 0xe0000000 default 0xe0000000
config MAX_CPUS config MAX_CPUS
@ -88,11 +88,11 @@ config SMM_RESERVED_SIZE
# #
config DCACHE_RAM_BASE config DCACHE_RAM_BASE
hex "Temporary RAM Base Address" hex
default 0xfef00000 default 0xfef00000
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
hex "Temporary RAM Size" hex
default 0x4000 default 0x4000
help help
The size of the cache-as-ram region required during bootblock The size of the cache-as-ram region required during bootblock