vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80
Update header files for FSP for Meteor Lake platform to version 3223_80, previous version being 3194_81. FSPM: 1. Add 'ROWHAMMER','RhSelect','McRefreshRate','Lfsr0Mask','Lfsr1Mask' UPDs 2. Add 'TmeExcludeBase','TmeExcludeSize','GenerateNewTmeKey' UPDs 3. Address offset changes BUG=b:287890130 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I4b8d0a3a87be7dc0d899298eb8e4e48905090e71 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75916 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Kilari Raasi
Subrata Banik
parent
c08b645ffc
commit
9c28ab1d1a
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@ -14,6 +14,7 @@
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#include <Guid/FspHeaderFile.h>
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#define BUILD_TIME_STAMP_SIZE 12
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//
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// FSP Header Data structure from FspHeader driver.
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//
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@ -2197,9 +2197,11 @@ typedef struct {
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**/
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UINT8 RMC;
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/** Offset 0x0B82 - Reserved
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/** Offset 0x0B82 - Row Hammering Prevention
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Enables/Disable Row Hammering Prevention
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$EN_DIS
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**/
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UINT8 Reserved55;
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UINT8 ROWHAMMER;
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/** Offset 0x0B83 - Dimm ODT Training
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Enables/Disable Dimm ODT Training
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@ -2233,7 +2235,7 @@ typedef struct {
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/** Offset 0x0B88 - Reserved
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**/
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UINT8 Reserved56[2];
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UINT8 Reserved55[2];
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/** Offset 0x0B8A - DIMM CA ODT Training
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Enable/Disable DIMM CA ODT Training
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@ -2243,7 +2245,7 @@ typedef struct {
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/** Offset 0x0B8B - Reserved
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**/
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UINT8 Reserved57[3];
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UINT8 Reserved56[3];
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/** Offset 0x0B8E - Read Vref Decap Training
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Enable/Disable Read Vref Decap Training
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@ -2265,7 +2267,7 @@ typedef struct {
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/** Offset 0x0B91 - Reserved
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**/
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UINT8 Reserved58[4];
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UINT8 Reserved57[4];
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/** Offset 0x0B95 - Duty Cycle Correction Training
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Enable/Disable Duty Cycle Correction Training
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@ -2275,7 +2277,7 @@ typedef struct {
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/** Offset 0x0B96 - Reserved
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**/
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UINT8 Reserved59[17];
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UINT8 Reserved58[17];
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/** Offset 0x0BA7 - ECC Support
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Enables/Disable ECC Support
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@ -2309,7 +2311,7 @@ typedef struct {
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/** Offset 0x0BB3 - Reserved
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**/
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UINT8 Reserved60;
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UINT8 Reserved59;
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/** Offset 0x0BB4 - IbeccProtectedRegionBases
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IBECC Protected Region Bases per IBECC instance
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@ -2387,9 +2389,11 @@ typedef struct {
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**/
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UINT8 ThrtCkeMinDefeat;
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/** Offset 0x0BEE - Reserved
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/** Offset 0x0BEE - Row Hammer Select
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Row Hammer Select
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0:Disable, 1:RFM, 2:pTRR
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**/
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UINT8 Reserved61;
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UINT8 RhSelect;
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/** Offset 0x0BEF - Exit On Failure (MRC)
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Enables/Disable Exit On Failure (MRC)
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@ -2399,7 +2403,7 @@ typedef struct {
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/** Offset 0x0BF0 - Reserved
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**/
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UINT8 Reserved62[4];
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UINT8 Reserved60[4];
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/** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
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ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
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@ -2658,7 +2662,7 @@ typedef struct {
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/** Offset 0x0C2B - Reserved
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**/
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UINT8 Reserved63[2];
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UINT8 Reserved61[2];
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/** Offset 0x0C2D - Rapl Power Floor Ch0
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Power budget ,range[255;0],(0= 5.3W Def)
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@ -2676,9 +2680,11 @@ typedef struct {
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**/
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UINT8 EnCmdRate;
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/** Offset 0x0C30 - Reserved
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/** Offset 0x0C30 - MC_REFRESH_RATE
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Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh
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0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh
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**/
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UINT8 Reserved64;
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UINT8 McRefreshRate;
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/** Offset 0x0C31 - Energy Performance Gain
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Enable/disable Energy Performance Gain. <b>0: Disable</b>; 1: Enable
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@ -2686,9 +2692,10 @@ typedef struct {
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**/
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UINT8 EpgEnable;
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/** Offset 0x0C32 - Reserved
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/** Offset 0x0C32 - RH pTRR LFSR0 Mask
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Row Hammer pTRR LFSR0 Mask, 1/2^(value)
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**/
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UINT8 Reserved65;
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UINT8 Lfsr0Mask;
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/** Offset 0x0C33 - User Manual Threshold
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Disabled: Predefined threshold will be used.\n
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@ -2706,7 +2713,7 @@ typedef struct {
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/** Offset 0x0C35 - Reserved
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**/
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UINT8 Reserved66;
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UINT8 Reserved62;
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/** Offset 0x0C36 - Power Down Mode
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This option controls command bus tristating during idle periods
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@ -2743,7 +2750,7 @@ typedef struct {
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/** Offset 0x0C3B - Reserved
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**/
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UINT8 Reserved67[8];
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UINT8 Reserved63[8];
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/** Offset 0x0C43 - Ask MRC to clear memory content
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Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
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@ -2758,7 +2765,7 @@ typedef struct {
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/** Offset 0x0C45 - Reserved
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**/
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UINT8 Reserved68;
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UINT8 Reserved64;
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/** Offset 0x0C46 - Post Code Output Port
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This option configures Post Code Output Port
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@ -2778,7 +2785,7 @@ typedef struct {
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/** Offset 0x0C4A - Reserved
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**/
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UINT8 Reserved69[2];
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UINT8 Reserved65[2];
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/** Offset 0x0C4C - BCLK RFI Frequency
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Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
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@ -2821,7 +2828,16 @@ typedef struct {
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/** Offset 0x0C62 - Reserved
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**/
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UINT8 Reserved70[13];
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UINT8 Reserved66[11];
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/** Offset 0x0C6D - RH pTRR LFSR1 Mask
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Row Hammer pTRR LFSR1 Mask, 1/2^(value)
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**/
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UINT8 Lfsr1Mask;
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/** Offset 0x0C6E - Reserved
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**/
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UINT8 Reserved67;
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/** Offset 0x0C6F - Command Pins Mapping
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BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
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@ -2837,7 +2853,7 @@ typedef struct {
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/** Offset 0x0C71 - Reserved
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**/
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UINT8 Reserved71[24];
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UINT8 Reserved68[24];
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/** Offset 0x0C89 - Skip external display device scanning
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Enable: Do not scan for external display device, Disable (Default): Scan external
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@ -2873,7 +2889,7 @@ typedef struct {
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/** Offset 0x0C8E - Reserved
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**/
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UINT8 Reserved72[2];
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UINT8 Reserved69[2];
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/** Offset 0x0C90 - PMR Size
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Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
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@ -2887,7 +2903,7 @@ typedef struct {
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/** Offset 0x0C95 - Reserved
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**/
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UINT8 Reserved73[143];
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UINT8 Reserved70[143];
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/** Offset 0x0D24 - TotalFlashSize
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Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
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@ -2903,7 +2919,7 @@ typedef struct {
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/** Offset 0x0D28 - Reserved
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**/
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UINT8 Reserved74[28];
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UINT8 Reserved71[28];
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/** Offset 0x0D44 - Smbus dynamic power gating
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Disable or Enable Smbus dynamic power gating.
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@ -2919,7 +2935,7 @@ typedef struct {
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/** Offset 0x0D46 - Reserved
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**/
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UINT8 Reserved75[2];
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UINT8 Reserved72[2];
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/** Offset 0x0D48 - SMBUS SPD Write Disable
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Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
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@ -2930,7 +2946,7 @@ typedef struct {
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/** Offset 0x0D49 - Reserved
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**/
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UINT8 Reserved76[34];
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UINT8 Reserved73[34];
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/** Offset 0x0D6B - HECI Timeouts
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0: Disable, 1: Enable (Default) timeout check for HECI
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@ -2983,7 +2999,7 @@ typedef struct {
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/** Offset 0x0D73 - Reserved
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**/
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UINT8 Reserved77[100];
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UINT8 Reserved74[100];
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/** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor
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AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
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@ -3006,7 +3022,7 @@ typedef struct {
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/** Offset 0x0DDA - Reserved
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**/
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UINT8 Reserved78[2];
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UINT8 Reserved75[2];
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/** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM
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Select RX pin muxing for SerialIo UART used for debug
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@ -3032,7 +3048,27 @@ typedef struct {
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/** Offset 0x0DEC - Reserved
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**/
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UINT8 Reserved79[188];
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UINT8 Reserved76[164];
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/** Offset 0x0E90 - TME Exclude Base Address
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TME Exclude Base Address.
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**/
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UINT64 TmeExcludeBase;
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/** Offset 0x0E98 - TME Exclude Size Value
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TME Exclude Size Value.
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**/
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UINT64 TmeExcludeSize;
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/** Offset 0x0EA0 - Generate New TME Key
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Enable: Generate New TME Key, Disable(Default): TME key determine by type of reset
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$EN_DIS
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**/
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UINT8 GenerateNewTmeKey;
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/** Offset 0x0EA1 - Reserved
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**/
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UINT8 Reserved77[7];
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} FSP_M_CONFIG;
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/** Fsp M UPD Configuration
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