Perform cleanup and file shrinkage of the AMD AGESA code.

Signed-off-by: Frank.Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/vendorcode/amd/agesa/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c

@@ -483,10 +483,10 @@ REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = {
     GMMx284C_Dimm0AddrMap_WIDTH + GMMx284C_Dimm1AddrMap_WIDTH
   },
   {
-    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x94_ADDRESS),
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x094_ADDRESS),
     GMMx284C_ADDRESS,
-    D18F2x94_BankSwizzleMode_OFFSET,
+    D18F2x094_BankSwizzleMode_OFFSET,
-    D18F2x94_BankSwizzleMode_WIDTH,
+    D18F2x094_BankSwizzleMode_WIDTH,
     GMMx284C_BankSwizzleMode_OFFSET,
     GMMx284C_BankSwizzleMode_WIDTH
   },

src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxStrapsInit.c

@@ -167,11 +167,9 @@ GfxStrapsInit (
   if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) {
     D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x0;
     D0F0x64_x1C.Field.RcieEn = 0x0;
-    D0F0x64_x1C.Field.PcieDis = 0x1;
   } else {
     D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x1;
     D0F0x64_x1C.Field.RcieEn = 0x1;
-    D0F0x64_x1C.Field.PcieDis = 0x0;
     //LN/ON A0 (MSI)
     GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessS3SaveWidth32, 0xffffffff, BIT2, GnbLibGetHeader (Gfx));
   }
@@ -182,7 +180,6 @@ GfxStrapsInit (
   }
   D0F0x64_x1C.Field.AudioEn = Gfx->GnbHdAudio;
   D0F0x64_x1C.Field.F0En = 0x1;
-//  D0F0x64_x1C.Field.F0BarEn = 0x1;  //Keep re-sizable bar disabled at 0 due to silicon bug
   D0F0x64_x1C.Field.RegApSize = 0x1;
 
   if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) {
@@ -315,10 +312,4 @@ GfxSetIdleVoltageMode (
   IN      GFX_PLATFORM_CONFIG   *Gfx
   )
 {
-  FCRxFF30_0191_STRUCT   FCRxFF30_0191;
-  NbSmuSrbmRegisterRead (FCRxFF30_0191_ADDRESS, &FCRxFF30_0191.Value, GnbLibGetHeader (Gfx));
-  FCRxFF30_0191.Field.GfxIdleVoltChgEn = 0x1;
-  FCRxFF30_0191.Field.GfxIdleVoltChgMode = (Gfx->GfxFusedOff || Gfx->UmaInfo.UmaMode != UMA_NONE) ? 0x0 : 0x1;
-  NbSmuSrbmRegisterWrite (FCRxFF30_0191_ADDRESS, &FCRxFF30_0191.Value, TRUE, GnbLibGetHeader (Gfx));
-
 }

src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c

@@ -158,10 +158,10 @@ GnbLpcDmaDeadlockPrevention (
   // For GPP Link core, enable special NP memory write protocol on the  processor side PCIE controller
   GnbLibPciIndirectRMW (
     NbPciAddress.AddressValue | D0F0xE0_ADDRESS,
-    CORE_SPACE (1, D0F0xE4_CORE_0010_ADDRESS),
+    CORE_SPACE (1, 0x10),
     AccessWidth32,
     0xFFFFFFFF,
-    1 << D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET,
+    1 << 9,
     StdHeader
   );
 
@@ -244,4 +244,4 @@ GnbLock (
     TRUE,
     StdHeader
     );
-}
+}

src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c

@@ -144,9 +144,9 @@ PcieLinkInitHotplug (
       );
     PcieRegisterWriteField (
       PcieEngineGetParentWrapper (Engine),
-      CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
+      CORE_SPACE (Engine->Type.Port.CoreId, 0x10),
-      D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET,
+      1,
-      D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH,
+      3,
       0x5,
       TRUE,
       Pcie

src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c

@@ -525,29 +525,22 @@ PcieTopologyInitSrbmReset (
   IN      PCIe_PLATFORM_CONFIG  *Pcie
   )
 {
-  D0F0xE4_WRAP_8063_STRUCT  D0F0xE4_WRAP_8063;
+  UINT32 pcireg;
-  D0F0xE4_WRAP_8063.Value = PcieRegisterRead (
+  UINT32 regmask = 0x7030;;
+  pcireg = PcieRegisterRead (
                                Wrapper,
-                               WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS),
+                               WRAP_SPACE (Wrapper->WrapId, 0x8063),
                                Pcie
                                );
   if (SrbmResetEnable) {
-    D0F0xE4_WRAP_8063.Field.ResetSrbm0En = 0x1;
+	pcireg |= regmask;
-    D0F0xE4_WRAP_8063.Field.ResetSrbm1En = 0x1;
-    D0F0xE4_WRAP_8063.Field.ResetSrbmNbEn = 0x1;
-    D0F0xE4_WRAP_8063.Field.ResetSrbmGfxEn = 0x1;
-    D0F0xE4_WRAP_8063.Field.ResetSrbmDcEn = 0x1;
   } else {
-    D0F0xE4_WRAP_8063.Field.ResetSrbm0En = 0x0;
+	pcireg &= ~(regmask);
-    D0F0xE4_WRAP_8063.Field.ResetSrbm1En = 0x0;
-    D0F0xE4_WRAP_8063.Field.ResetSrbmNbEn = 0x0;
-    D0F0xE4_WRAP_8063.Field.ResetSrbmGfxEn = 0x0;
-    D0F0xE4_WRAP_8063.Field.ResetSrbmDcEn = 0x0;
   }
   PcieRegisterWrite (
     Wrapper,
-    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS),
+    WRAP_SPACE (Wrapper->WrapId, 0x8063),
-    D0F0xE4_WRAP_8063.Value,
+    pcireg,
     FALSE,
     Pcie
     );

src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c

@@ -424,9 +424,9 @@ PcieLockRegisters (
     for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
       PcieRegisterWriteField (
         Wrapper,
-        CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS),
+        CORE_SPACE (CoreId, 0x10),
-        D0F0xE4_CORE_0010_HwInitWrLock_OFFSET,
+        0,
-        D0F0xE4_CORE_0010_HwInitWrLock_WIDTH,
+        1,
         0x1,
         TRUE,
         Pcie

src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.c

@@ -112,14 +112,13 @@ PciePortsVisibilityControl (
 PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = {
   {
     D0F0xE4_CORE_0020_ADDRESS,
-    D0F0xE4_CORE_0020_CiRcOrderingDis_MASK |
+    D0F0xE4_CORE_0020_CiRcOrderingDis_MASK,
-    D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK,
     (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET)
   },
   {
-    D0F0xE4_CORE_0010_ADDRESS,
+    0x10,
-    D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_MASK,
+    0x1c00,
-    (0x4 << D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_OFFSET)
+    (0x4 << 10)
   },
   {
     D0F0xE4_CORE_001C_ADDRESS,
@@ -149,8 +148,7 @@ PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = {
   },
   {
     D0F0xE4_CORE_00B0_ADDRESS,
-    D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK |
+    D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK, 
-    D0F0xE4_CORE_00B0_StrapF0AerEn_MASK,
     (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET)
   }
 };