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soc/intel/alderlake: Fix processor hang while plug unplug of TBT device 

Processor hang is observed while hot plug unplug of TBT device. BIOS
should execute TBT PCIe RP RTD3 flow based on the value of
TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if
BIT30 in TBT FW version is not set.

BUG=b:194880254

Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56503
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sugnan Prabhu S 2021-07-22 10:35:50 +05:30 committed by Tim Wawrzynczak
parent 7517c39c9e
commit 9c348a7b7e
2 changed files with 10 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/soc/intel/alderlake/acpi/tcss.asl
View File

@ -555,12 +555,13 @@ Scope (\_SB.PCI0)
Printf("TDM0 does not exist.")
} Else {
If (\_SB.PCI0.TDM0.STAT == 1) {
If (\_SB.PCI0.TDM0.INFR != 1) {
Return
}
/* DMA0 is not in D3Cold now. */
\_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */
If (\_SB.PCI0.TDM0.IF30 != 1) {
Return
}
Printf("Push TBT RPs to D3Cold together")
If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
/* Put RP0 to D3 cold. */
@ -613,12 +614,13 @@ Scope (\_SB.PCI0)
Printf("TDM1 does not exist.")
} Else {
If (\_SB.PCI0.TDM1.STAT == 1) {
If (\_SB.PCI0.TDM1.INFR != 1) {
Return
}
/* DMA1 is not in D3Cold now */
\_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */
If (\_SB.PCI0.TDM1.IF30 != 1) {
Return
}
Printf("Push TBT RPs to D3Cold together")
If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
/* Put RP2 to D3 cold. */

3
src/soc/intel/alderlake/acpi/tcss_dma.asl
View File

@ -11,7 +11,8 @@ Field (DPME, AnyAcc, NoLock, Preserve)
, 6,
PMES, 1, /* 15, PME_STATUS */
Offset(0xC8), /* 0xC8, TBT NVM FW Revision */
, 31,
, 30,
IF30, 1, /* ITBT FW Version Bit30 */
INFR, 1, /* TBT NVM FW Ready */
Offset(0xEC), /* 0xEC, TBT TO PCIE Register */
TB2P, 32, /* TBT to PCIe */