mb/google/brya: Configure WWAN GPIO early
In order to meet timing requirement of WWAN reseting it in early GPIOs and asserting Reset GPIO in ramstage BUG=b:180166408 TEST=Build and boot Brya system and verify enumeration of L850 and FM350 devices Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: Id6d69696b6c645eec3fa314a608c69214bafba82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54912 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -159,7 +159,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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/* E0 : SATAXPCIE0 ==> WWAN_PERST_L */
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PAD_CFG_GPO(GPP_E0, 1, DEEP),
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PAD_CFG_GPO(GPP_E0, 1, PLTRST),
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/* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_E1, NONE, DEEP),
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/* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
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@ -367,6 +367,8 @@ static const struct pad_config gpio_table[] = {
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */
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PAD_CFG_GPO(GPP_A12, 1, DEEP),
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
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@ -384,11 +386,12 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPO(GPP_D1, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* E0 : SATAXPCIE0 ==> WWAN_PERST_L */
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PAD_CFG_GPO(GPP_E0, 0, DEEP),
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/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_E13, NONE, DEEP),
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/* E16 : RSVD_TP ==> WWAN_RST_L */
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/* E16 : RSVD_TP ==> WWAN_RST_L
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* To meet timing constrains - drive reset low.
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* Deasserted in ramstage.
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*/
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PAD_CFG_GPO(GPP_E16, 0, DEEP),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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