From 9c4514ba14e29550041e4c18aaafdd7c0bbc097e Mon Sep 17 00:00:00 2001 From: Adam Mills Date: Wed, 10 Aug 2022 15:49:00 +1000 Subject: [PATCH] soc/intel/alderlake/acpi: Changing USB ports indexing. xhci.asl places the SS ports at 11-14, following HS ports 1-10. However, for Nissa, the kernel detects 12 HS ports 1-12 and 4 SS ports at 13-16, resulting in the PLD intended for SS ports 1 and 2 being associated with HS ports 11 and 12. Changing the asl for SS to 13-16 makes locations associate correctly and peering work. BUG=b:234544025 BRANCH=firmware-brya-14505.B TEST=manually verified on Nissa and Brya devices Change-Id: I57aef771a7ff086b71a9e90b81e1a3635f832b2f Signed-off-by: Adam Mills Reviewed-on: https://review.coreboot.org/c/coreboot/+/66590 Reviewed-by: Tim Wawrzynczak Reviewed-by: Sam McNally Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/acpi/xhci.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl index 34ff612143..b44bc671f7 100644 --- a/src/soc/intel/alderlake/acpi/xhci.asl +++ b/src/soc/intel/alderlake/acpi/xhci.asl @@ -74,10 +74,10 @@ Device (XHCI) Device (HS09) { Name (_ADR, 9) } Device (HS10) { Name (_ADR, 10) } /* USB3 */ - Device (SS01) { Name (_ADR, 11) } - Device (SS02) { Name (_ADR, 12) } - Device (SS03) { Name (_ADR, 13) } - Device (SS04) { Name (_ADR, 14) } + Device (SS01) { Name (_ADR, 13) } + Device (SS02) { Name (_ADR, 14) } + Device (SS03) { Name (_ADR, 15) } + Device (SS04) { Name (_ADR, 16) } } #endif }