From 9c4ae9131ce5f391c97f9ce4f78fce0e1697d9b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Sat, 29 Oct 2022 18:00:18 +0200 Subject: [PATCH] soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using a HECI message that needs to be sent before EOP. Make the option configurable to allow soft ME disable on alderlake. Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Signed-off-by: Michał Kopeć Reviewed-on: https://review.coreboot.org/c/coreboot/+/69953 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Subrata Banik --- src/soc/intel/alderlake/Kconfig | 4 +++- src/soc/intel/common/block/cse/Kconfig | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 08d4132f61..5b624d8ae1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -117,7 +117,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_CSE_SEND_EOP_EARLY select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select HAVE_INTEL_COMPLIANCE_TEST_MODE @@ -459,6 +458,9 @@ config USE_COREBOOT_MP_INIT endchoice +config SOC_INTEL_CSE_SEND_EOP_EARLY + default y + if STITCH_ME_BIN config CSE_BPDT_VERSION diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 2962a1472e..82022b190b 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -46,7 +46,7 @@ config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR to make `HECI1` device disable using private configuration register (PCR) write. config SOC_INTEL_CSE_SEND_EOP_EARLY - bool + bool "CSE send EOP early" depends on SOC_INTEL_COMMON_BLOCK_CSE help Use this config to send End Of Post (EOP) earlier through SoC code in order to