Delete mainboard/google/cheza
Work on this mainboard was abandoned and never finished. It's not really usable in its current state, so let's get rid of it. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Julius Werner
parent
42b1d3fccf
commit
9c50462fd7
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@ -20,7 +20,6 @@
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- Tricky (Dell Chromebox 3010)
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- Zako (HP Chromebox G1)
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- Butterfly (HP Pavilion Chromebook 14)
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- Cheza
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- Banon (Acer Chromebook 15 (CB3-532))
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- Celes (Samsung Chromebook 3)
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- Cyan (Acer Chromebook R11 (C738T))
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@ -1,3 +0,0 @@
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CONFIG_LP_CHROMEOS=y
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CONFIG_LP_ARCH_ARM64=y
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CONFIG_LP_TIMER_ARM64_ARCH=y
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@ -1,46 +0,0 @@
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config BOARD_GOOGLE_CHEZA_COMMON # Umbrella option to be selected by variants
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def_bool n
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if BOARD_GOOGLE_CHEZA_COMMON
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select COMMON_CBFS_SPI_WRAPPER
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_RTC
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select EC_GOOGLE_CHROMEEC_SPI
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select RTC
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select SOC_QUALCOMM_SDM845
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select SPI_FLASH
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select SPI_FLASH_WINBOND
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_HAS_SPI_TPM_CR50
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_VBNV_FLASH
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config MAINBOARD_DIR
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string
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default "google/cheza"
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config DRIVER_TPM_SPI_BUS
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hex
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default 0x5
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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default 0xa
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##########################################################
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#### Update below when adding a new derivative board. ####
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##########################################################
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config MAINBOARD_PART_NUMBER
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string
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default "Cheza" if BOARD_GOOGLE_CHEZA
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endif # BOARD_GOOGLE_CHEZA_COMMON
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@ -1,4 +0,0 @@
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config BOARD_GOOGLE_CHEZA
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bool "Cheza"
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select BOARD_GOOGLE_CHEZA_COMMON
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@ -1,20 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += boardid.c
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bootblock-y += chromeos.c
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bootblock-y += bootblock.c
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bootblock-y += reset.c
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verstage-y += boardid.c
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verstage-y += chromeos.c
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verstage-y += reset.c
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romstage-y += boardid.c
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romstage-y += chromeos.c
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romstage-y += romstage.c
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romstage-y += reset.c
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ramstage-y += boardid.c
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ramstage-y += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += reset.c
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@ -1,17 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H
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#define __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H
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#include <gpio.h>
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#include <soc/gpio.h>
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#define GPIO_EC_IN_RW GPIO(11)
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#define GPIO_AP_EC_INT GPIO(122)
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#define GPIO_AP_SUSPEND GPIO(126)
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#define GPIO_WP_STATE GPIO(128)
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#define GPIO_H1_AP_INT GPIO(129)
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void setup_chromeos_gpios(void);
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#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H */
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@ -1,6 +0,0 @@
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Vendor name: Google
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Board name: Cheza Qualcomm SDM845 reference board
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Category: eval
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -1,37 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <boardid.h>
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#include <gpio.h>
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uint32_t board_id(void)
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{
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const gpio_t pins[] = {[2] = GPIO(51), [1] = GPIO(62), [0] = GPIO(38)};
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static uint32_t id = UNDEFINED_STRAPPING_ID;
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if (id == UNDEFINED_STRAPPING_ID)
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id = gpio_base2_value(pins, ARRAY_SIZE(pins));
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return id;
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}
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uint32_t ram_code(void)
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{
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const gpio_t pins[] = {[1] = GPIO(147), [0] = GPIO(146)};
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static uint32_t id = UNDEFINED_STRAPPING_ID;
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if (id == UNDEFINED_STRAPPING_ID)
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id = gpio_base2_value(pins, ARRAY_SIZE(pins));
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return id;
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}
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uint32_t sku_id(void)
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{
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const gpio_t pins[] = {[1] = GPIO(113), [0] = GPIO(79)};
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static uint32_t id = UNDEFINED_STRAPPING_ID;
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if (id == UNDEFINED_STRAPPING_ID)
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id = gpio_base2_value(pins, ARRAY_SIZE(pins));
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return id;
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}
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@ -1,9 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include "board.h"
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void bootblock_mainboard_init(void)
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{
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setup_chromeos_gpios();
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}
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@ -1,33 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <boot/coreboot_tables.h>
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#include <bootmode.h>
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#include "board.h"
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int get_write_protect_state(void)
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{
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return !gpio_get(GPIO_WP_STATE);
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}
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void setup_chromeos_gpios(void)
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{
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gpio_input_pullup(GPIO_EC_IN_RW);
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gpio_input_pullup(GPIO_AP_EC_INT);
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gpio_output(GPIO_AP_SUSPEND, 1);
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gpio_input(GPIO_WP_STATE);
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gpio_input_pullup(GPIO_H1_AP_INT);
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}
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW),
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"EC in RW"},
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{GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT),
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"EC interrupt"},
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{GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT),
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"TPM interrupt"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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@ -1,42 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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FLASH@0x0 8M {
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WP_RO 4M {
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RO_SECTION 0x184000 {
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BOOTBLOCK 96K
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COREBOOT(CBFS)
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#TODO: Move FMAP to 2M or 3M once FSG can be smaller
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FMAP@0x180000 0x1000
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GBB 0x2f00
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RO_FRID 0x100
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}
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RO_VPD(PRESERVE) 16K
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RO_DDR_TRAINING(PRESERVE) 8K
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RO_LIMITS_CFG(PRESERVE) 4K
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RO_FSG(PRESERVE)
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}
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RW_VPD(PRESERVE) 32K
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RW_NVRAM(PRESERVE) 16K
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RW_DDR_TRAINING(PRESERVE) 8K
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RW_LIMITS_CFG(PRESERVE) 4K
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RW_ELOG(PRESERVE) 4K
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RW_SHARED 4K {
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SHARED_DATA
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}
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RW_SECTION_A 1280K {
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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RW_FWID_A 256
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}
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RW_SECTION_B 1280K {
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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RW_FWID_B 256
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}
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RW_LEGACY(CBFS)
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}
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@ -1,5 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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chip soc/qualcomm/sdm845
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device cpu_cluster 0 on end
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end
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@ -1,37 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <gpio.h>
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#include <soc/usb.h>
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static struct usb_board_data usb1_board_data = {
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.pll_bias_control_2 = 0x28,
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.imp_ctrl1 = 0x08,
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.port_tune1 = 0x20,
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};
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static void setup_usb(void)
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{
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/*
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* Primary USB is used only for DP functionality on cheza platform.
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* Hence Setting up only Secondary USB DWC3 controller.
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*/
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setup_usb_host1(&usb1_board_data);
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gpio_output(GPIO(120), 1); /* Deassert HUB_RST_L to enable hub. */
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}
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static void mainboard_init(struct device *dev)
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{
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setup_usb();
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->init = &mainboard_init;
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}
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struct chip_operations mainboard_ops = {
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.name = CONFIG_MAINBOARD_PART_NUMBER,
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.enable_dev = mainboard_enable,
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};
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@ -1,11 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <ec/google/chromeec/ec.h>
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#include <reset.h>
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/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage),
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but this works well enough for our purposes. */
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void do_board_reset(void)
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{
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google_chromeec_reboot(0, EC_REBOOT_COLD, 0);
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}
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@ -1,22 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/stages.h>
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#include <soc/usb.h>
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#include <soc/qclib_common.h>
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static void prepare_usb(void)
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{
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/*
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* Do DWC3 core and phy reset. Kick these resets
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* off early so they get at least 1ms to settle.
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*/
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reset_usb1();
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}
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void platform_romstage_main(void)
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{
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prepare_usb();
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/* QCLib: DDR init & train */
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qclib_load_and_run();
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}
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