mb/google/drallion: Fine tune touch screen power sequence
Follow HW change to use GPP_D15 as TS_RST. And change GPP_B21 from pltrst to deep in order to met power off timing. BUG=b:143733039 TEST=Check touch screen is functional in s0 and resume from s0ix Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/38665 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -336,9 +336,15 @@ chip soc/intel/cannonlake
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register "generic.desc" = ""Wacom Touchscreen""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)"
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register "generic.probed" = "1"
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register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
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register "generic.reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
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register "generic.reset_delay_ms" = "10"
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register "generic.reset_off_delay_ms" = "5"
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register "generic.stop_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
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register "generic.stop_delay_ms" = "20"
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register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
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register "generic.enable_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
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register "generic.enable_delay_ms" = "55"
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register "generic.has_power_resource" = "1"
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register "generic.disable_gpio_export_in_crs" = "1"
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@ -352,6 +358,10 @@ chip soc/intel/cannonlake
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register "generic.desc" = ""ELAN Touchscreen""
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register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
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register "generic.reset_delay_ms" = "10"
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register "generic.reset_off_delay_ms" = "5"
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register "generic.stop_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
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register "generic.stop_delay_ms" = "10"
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@ -369,6 +379,9 @@ chip soc/intel/cannonlake
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register "desc" = ""Melfas Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
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register "reset_delay_ms" = "10"
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register "reset_off_delay_ms" = "5"
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register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
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register "stop_delay_ms" = "10"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
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@ -78,7 +78,7 @@ static const struct pad_config gpio_table[] = {
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/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
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/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */
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/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE),
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/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, PLTRST), /* PCH_3.3V_TS_EN */
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/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* PCH_3.3V_TS_EN */
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/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
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/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K),
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@ -124,7 +124,7 @@ static const struct pad_config gpio_table[] = {
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/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1),
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/* ISH_CPU_UART0_TX */
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/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
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/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE),
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/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */
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/* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST),
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/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */
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/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
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