nb/intel/sandybridge: Make the mainboard_rcba_config hook optional

This also changes the name to mainboard_late_rcba_config to better
reflect what it does.

This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.

Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/apple/macbookair4_2/romstage.c

@@ -27,7 +27,7 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	/* Disable devices.  */
 	RCBA32(0x3414) = 0x00000020;

src/mainboard/asrock/b75pro3-m/romstage.c

@@ -27,10 +27,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },

src/mainboard/asus/h61m-cs/romstage.c

@@ -31,10 +31,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },

src/mainboard/asus/maximus_iv_gene-z/romstage.c

@@ -44,10 +44,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);

src/mainboard/asus/p8h61-m_lx/romstage.c

@@ -47,10 +47,6 @@ void pch_enable_lpc(void)
 			CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/p8h61-m_pro/romstage.c

@@ -32,10 +32,6 @@ void pch_enable_lpc(void)
 			KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },

src/mainboard/asus/p8z77-m_pro/romstage.c

@@ -34,10 +34,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	/* {enable, current, oc_pin} */
 	{ 1, 2, 0 }, /* Port 0: USB3 front internal header, top */

src/mainboard/compulab/intense_pc/romstage.c

@@ -39,7 +39,7 @@ void pch_enable_lpc(void)
 #endif
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	RCBA32(0x3414) = 0x00000000;
 }

src/mainboard/gigabyte/ga-b75m-d3h/romstage.c

@@ -87,7 +87,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 	read_spd(&spd[3], 0x53, id_only);
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	/* Enable HECI */
 	RCBA32(FD2) &= ~0x2;

src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c

@@ -27,10 +27,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },

src/mainboard/google/butterfly/romstage.c

@@ -35,7 +35,7 @@ void pch_enable_lpc(void)
 	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	u32 reg32;
 

src/mainboard/google/link/romstage.c

@@ -39,7 +39,7 @@ void pch_enable_lpc(void)
 			   GAMEL_LPC_EN | COMA_LPC_EN);
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)

src/mainboard/google/parrot/romstage.c

@@ -30,7 +30,7 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	u32 reg32;
 

src/mainboard/google/stout/romstage.c

@@ -43,7 +43,7 @@ void pch_enable_lpc(void)
 			CNF1_LPC_EN | FDD_LPC_EN);
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	u32 reg32;
 

src/mainboard/hp/2570p/romstage.c

@@ -24,10 +24,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
 	{ 0, 1, 0 },

src/mainboard/hp/2760p/romstage.c

@@ -23,10 +23,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
 	{ 1, 1, 0 },

src/mainboard/hp/8460p/romstage.c

@@ -27,10 +27,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 }, /* USB0, eSATA */
 	{ 1, 0, 0 }, /* USB charger */

src/mainboard/hp/8470p/romstage.c

@@ -26,10 +26,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
 	{ 1, 1, 0 },

src/mainboard/hp/8770w/romstage.c

@@ -27,10 +27,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 }, /* Dock USB3.0 */
 	{ 1, 1, 0 }, /* Conn */

src/mainboard/hp/compaq_8200_elite_sff/romstage.c

@@ -31,10 +31,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 	{ 1, 0, -1 },

src/mainboard/hp/folio_9470m/romstage.c

@@ -25,10 +25,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 }, /* SSP1: dock */
 	{ 1, 1, 0 }, /* SSP2: left, EHCI Debug */

src/mainboard/hp/revolve_810_g1/romstage.c

@@ -28,7 +28,7 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	RCBA32(BUC) = 0x00000000;
 }

src/mainboard/hp/z220_sff_workstation/romstage.c

@@ -31,10 +31,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },

src/mainboard/intel/dcp847ske/early_southbridge.c

@@ -31,7 +31,7 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	/* Disable devices */
 	RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI;

src/mainboard/intel/emeraldlake2/romstage.c

@@ -43,11 +43,6 @@ void pch_enable_lpc(void)
 	}
 }
 
-void mainboard_rcba_config(void)
-{
-	southbridge_configure_default_intmap();
-}
-
 void mainboard_config_superio(void)
 {
 	const u16 port = SIO_PORT;

src/mainboard/kontron/ktqm77/romstage.c

@@ -43,7 +43,7 @@ void pch_enable_lpc(void)
 			   COMA_LPC_EN | COMB_LPC_EN);
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	u32 reg32;
 

src/mainboard/lenovo/l520/romstage.c

@@ -26,10 +26,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 	{ 1, 0, -1 },

src/mainboard/lenovo/s230u/romstage.c

@@ -42,7 +42,7 @@ void pch_enable_lpc(void)
 		ec_mm_set_bit(0x3b, 4);
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	/* Disable devices.  */
 	RCBA32(BUC) = 0x00000020;

src/mainboard/lenovo/t420/romstage.c

@@ -54,10 +54,6 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 // OC3 set in bios to port 2-7, OC7 set in bios to port 10-13
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1,  0 }, /* P0: system port 4, OC0 */

src/mainboard/lenovo/t420s/romstage.c

@@ -54,10 +54,6 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 0, 1, -1 }, /* P0 empty */
 	{ 1, 1,  1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */

src/mainboard/lenovo/t430/romstage.c

@@ -53,10 +53,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 /* FIXME: used T530 values here */
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1,  0 },

src/mainboard/lenovo/t430s/romstage.c

@@ -24,10 +24,6 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/mainboard/lenovo/t520/romstage.c

@@ -56,10 +56,6 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 }, /* P0 left dual conn, OC 0 */
 	{ 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */

src/mainboard/lenovo/t530/romstage.c

@@ -56,10 +56,6 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 void mainboard_early_init(int s3resume)
 {
 	hybrid_graphics_init();

src/mainboard/lenovo/x131e/romstage.c

@@ -24,10 +24,6 @@ void pch_enable_lpc(void)
 {
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{1, 1, 0},	/* P0: USB 3.0 1 (OC0) */
 	{1, 1, 0},	/* P1: USB 3.0 2 (OC0) */

src/mainboard/lenovo/x1_carbon_gen1/romstage.c

@@ -68,10 +68,6 @@ static uint8_t *get_spd_data(int spd_index)
 	return spd_file + spd_index * 256;
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 {
 	uint8_t *memory;

src/mainboard/lenovo/x220/romstage.c

@@ -32,10 +32,6 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 	struct pei_data pei_data_template = {

src/mainboard/lenovo/x230/romstage.c

@@ -29,10 +29,6 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 }, /* P0 (left, fan side), OC 0 */
 	{ 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */

src/mainboard/msi/ms7707/romstage.c

@@ -28,10 +28,6 @@ void pch_enable_lpc(void)
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16);
 }
 
-void mainboard_rcba_config(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{1, 0, 0},
 	{1, 0, 0},

src/mainboard/roda/rv11/romstage.c

@@ -16,7 +16,7 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	u32 reg32;
 

src/mainboard/samsung/lumpy/romstage.c

@@ -51,7 +51,7 @@ void pch_enable_lpc(void)
 #endif
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)

src/mainboard/samsung/stumpy/romstage.c

@@ -62,7 +62,7 @@ void pch_enable_lpc(void)
 #endif
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)

src/mainboard/sapphire/pureplatinumh61/romstage.c

@@ -26,7 +26,7 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
 }
 
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	/* Disable devices.  */
 	RCBA32(0x3414) = 0x00000020;

src/northbridge/intel/sandybridge/romstage.c

@@ -34,6 +34,10 @@ __weak void mainboard_early_init(int s3_resume)
 {
 }
 
+__weak void mainboard_late_rcba_config(void)
+{
+}
+
 static void early_pch_reset_pmcon(void)
 {
 	u8 reg8;
@@ -100,7 +104,7 @@ void mainboard_romstage_entry(void)
 
 	southbridge_configure_default_intmap();
 	southbridge_rcba_config();
-	mainboard_rcba_config();
+	mainboard_late_rcba_config();
 
 	post_code(0x3d);
 

src/southbridge/intel/bd82x6x/pch.h

@@ -72,7 +72,9 @@ int smbus_read_byte(unsigned int device, unsigned int address);
 void early_thermal_init(void);
 void southbridge_configure_default_intmap(void);
 void southbridge_rcba_config(void);
-void mainboard_rcba_config(void);
+/* Optional mainboard hook to do additional configuration
+   on the RCBA config space. It is called after the raminit. */
+void mainboard_late_rcba_config(void);
 void early_pch_init_native(void);
 void early_pch_init(void);
 void early_pch_init_native_dmi_pre(void);