soc/intel/meteorlake: Hook up UPD LowerBasicMemTestSize
Hook the newly exposed LowerBasicMemTestSize UPD up so that boards can configure it via devicetree. BUG=b:301441204 TEST=Verified by enabling/disabling the UPD on google/rex. Change-Id: Iec466aeaebd72f222d97f720a85bbb8c27e26325 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78066 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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@ -439,6 +439,13 @@ struct soc_intel_meteorlake_config {
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/* Gear Selection for SAGV points. 0: Auto, 1: Gear 1, 2: Gear 2, 4: Gear 4 */
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uint8_t sagv_gear[MAX_SAGV_POINTS];
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/*
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* Enable or Disable Reduced BasicMemoryTest size.
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* Default is set to 0.
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* Set this to 1 in order to reduce BasicMemoryTest size
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*/
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bool lower_basic_mem_test_size;
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};
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typedef struct soc_intel_meteorlake_config config_t;
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@ -158,6 +158,7 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
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m_cfg->RMT = config->rmt;
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/* Enable MRC Fast Boot */
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m_cfg->MrcFastBoot = 1;
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m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size;
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}
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static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
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