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mainboard/google: Remove use of __PRE_RAM__ 

Change-Id: I2ebeb393e4a5a4bfac8a37a877d067aca484ca2e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kyösti Mälkki 2019-08-17 05:28:38 +03:00
parent 157b189f6b
commit 9c5a9bba8e
5 changed files with 5 additions and 20 deletions
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5
src/mainboard/google/auron/chromeos.c
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@ -13,15 +13,13 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <boot/coreboot_tables.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#include <soc/gpio.h> #include <soc/gpio.h>
/* SPI Write protect is GPIO 16 */ /* SPI Write protect is GPIO 16 */
#define CROS_WP_GPIO 58 #define CROS_WP_GPIO 58
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
void fill_lb_gpios(struct lb_gpios *gpios) void fill_lb_gpios(struct lb_gpios *gpios)
{ {
struct lb_gpio chromeos_gpios[] = { struct lb_gpio chromeos_gpios[] = {
@ -33,7 +31,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
}; };
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
} }
#endif
int get_write_protect_state(void) int get_write_protect_state(void)
{ {

5
src/mainboard/google/link/chromeos.c
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@ -15,13 +15,11 @@
#include <string.h> #include <string.h>
#include <bootmode.h> #include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
void fill_lb_gpios(struct lb_gpios *gpios) void fill_lb_gpios(struct lb_gpios *gpios)
{ {
struct lb_gpio chromeos_gpios[] = { struct lb_gpio chromeos_gpios[] = {
@ -41,7 +39,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
}; };
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
} }
#endif
int get_write_protect_state(void) int get_write_protect_state(void)
{ {

5
src/mainboard/google/rambi/chromeos.c
View File

@ -14,15 +14,13 @@
*/ */
#include <bootmode.h> #include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ /* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */
#define WP_STATUS_PAD 36 #define WP_STATUS_PAD 36
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
void fill_lb_gpios(struct lb_gpios *gpios) void fill_lb_gpios(struct lb_gpios *gpios)
{ {
struct lb_gpio chromeos_gpios[] = { struct lb_gpio chromeos_gpios[] = {
@ -33,7 +31,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
}; };
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
} }
#endif
int get_write_protect_state(void) int get_write_protect_state(void)
{ {

5
src/mainboard/google/slippy/chromeos.c
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@ -14,13 +14,11 @@
*/ */
#include <bootmode.h> #include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
void fill_lb_gpios(struct lb_gpios *gpios) void fill_lb_gpios(struct lb_gpios *gpios)
{ {
struct lb_gpio chromeos_gpios[] = { struct lb_gpio chromeos_gpios[] = {
@ -31,7 +29,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
}; };
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
} }
#endif
int get_write_protect_state(void) int get_write_protect_state(void)
{ {

5
src/mainboard/intel/wtm2/chromeos.c
View File

@ -14,6 +14,7 @@
*/ */
#include <bootmode.h> #include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <soc/gpio.h> #include <soc/gpio.h>
@ -22,9 +23,6 @@
/* Compile-time settings for recovery mode. */ /* Compile-time settings for recovery mode. */
#define REC_MODE_SETTING 0 #define REC_MODE_SETTING 0
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
void fill_lb_gpios(struct lb_gpios *gpios) void fill_lb_gpios(struct lb_gpios *gpios)
{ {
struct lb_gpio chromeos_gpios[] = { struct lb_gpio chromeos_gpios[] = {
@ -35,7 +33,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
}; };
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
} }
#endif
int get_recovery_mode_switch(void) int get_recovery_mode_switch(void)
{ {