nb/i945/gma.c: use IS_ENABLED instead of #if, #endif
Change-Id: Ib58126e1c9001ed679e161d6d06241fac762bdb3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17049 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Arthur Heymans
Martin Roth
parent
fe517f635b
commit
9c5fc62f96
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@ -46,8 +46,6 @@
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#define BASE_FREQUENCY 100000
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#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
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static int gtt_setup(void *mmiobase)
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{
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unsigned long PGETBL_save;
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@ -218,19 +216,21 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
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BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
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(pixel_n + 2) / (pixel_p1 * pixel_p2));
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#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
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write32(pmmio + PF_WIN_POS(0), 0);
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write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
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write32(pmmio + PFIT_CONTROL, PFIT_ENABLE | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE | VERT_AUTO_SCALE);
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#else
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/* Disable panel fitter (we're in native resolution). */
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write32(pmmio + PF_CTL(0), 0);
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write32(pmmio + PF_WIN_SZ(0), 0);
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write32(pmmio + PF_WIN_POS(0), 0);
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write32(pmmio + PFIT_PGM_RATIOS, 0);
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write32(pmmio + PFIT_CONTROL, 0);
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#endif
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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/* Disable panel fitter (we're in native resolution). */
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write32(pmmio + PF_CTL(0), 0);
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write32(pmmio + PF_WIN_SZ(0), 0);
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write32(pmmio + PF_WIN_POS(0), 0);
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write32(pmmio + PFIT_PGM_RATIOS, 0);
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write32(pmmio + PFIT_CONTROL, 0);
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} else {
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write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
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write32(pmmio + PF_WIN_POS(0), 0);
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write32(pmmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
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write32(pmmio + PFIT_CONTROL, PFIT_ENABLE
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| (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE
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| VERT_AUTO_SCALE);
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}
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mdelay(1);
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@ -279,11 +279,13 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
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((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
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| (vactive + bottom_border + vfront_porch - 1));
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#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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write32(pmmio + PIPESRC(1), (639 << 16) | 399);
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#else
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write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1));
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#endif
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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write32(pmmio + PIPESRC(1), ((hactive - 1) << 16)
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| (vactive - 1));
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} else {
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write32(pmmio + PIPESRC(1), (639 << 16) | 399);
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}
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mdelay(1);
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write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16));
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@ -368,21 +370,21 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
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else
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printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n");
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#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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vga_misc_write(0x67);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n",
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(void *)pgfx, hactive * vactive * 4);
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memset((void *)pgfx, 0x00, hactive * vactive * 4);
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write32(pmmio + DSPCNTR(0), DISPPLANE_SEL_PIPE_B);
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set_vbe_mode_info_valid(&edid, pgfx);
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} else {
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vga_misc_write(0x67);
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write32(pmmio + VGACNTRL, 0x02c4008e | VGA_PIPE_B_SELECT);
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write32(pmmio + DSPCNTR(0), DISPPLANE_SEL_PIPE_B);
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write32(pmmio + VGACNTRL, 0x02c4008e
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| VGA_PIPE_B_SELECT);
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vga_textmode_init();
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#else
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printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n",
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(void *)pgfx, hactive * vactive * 4);
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memset((void *)pgfx, 0x00, hactive * vactive * 4);
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set_vbe_mode_info_valid(&edid, pgfx);
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#endif
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vga_textmode_init();
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}
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return 0;
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}
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@ -575,7 +577,6 @@ static int probe_edid(u8 *pmmio, u8 slave)
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return 1;
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}
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#endif
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static void gma_func0_init(struct device *dev)
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{
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@ -593,49 +594,50 @@ static void gma_func0_init(struct device *dev)
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pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER
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| PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
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#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
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/* PCI Init, will run VBIOS */
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pci_dev_init(dev);
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#endif
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#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
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/* This should probably run before post VBIOS init. */
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printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
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void *mmiobase;
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u32 iobase, graphics_base;
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struct northbridge_intel_i945_config *conf = dev->chip_info;
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iobase = dev->resource_list[1].base;
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mmiobase = (void *)(uintptr_t)dev->resource_list[0].base;
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graphics_base = dev->resource_list[2].base;
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printk(BIOS_SPEW, "GMADR = 0x%08x GTTADR = 0x%08x\n",
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pci_read_config32(dev, GMADR),
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pci_read_config32(dev, GTTADR)
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);
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int err;
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/* probe if VGA is connected and alway run */
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/* VGA init if no LVDS is connected */
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if (!probe_edid(mmiobase, 3) || probe_edid(mmiobase, 2))
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err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf,
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iobase, mmiobase, graphics_base);
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else
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err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf,
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iobase, mmiobase, graphics_base);
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if (err == 0)
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gfx_set_init_done(1);
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/* Linux relies on VBT for panel info. */
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if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) {
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generate_fake_intel_oprom(&conf->gfx, dev,
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"$VBT CALISTOGA");
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if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
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/* PCI Init, will run VBIOS */
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pci_dev_init(dev);
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}
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if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) {
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generate_fake_intel_oprom(&conf->gfx, dev,
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"$VBT LAKEPORT-G");
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if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
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/* This should probably run before post VBIOS init. */
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printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
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void *mmiobase;
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u32 iobase, graphics_base;
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struct northbridge_intel_i945_config *conf = dev->chip_info;
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iobase = dev->resource_list[1].base;
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mmiobase = (void *)(uintptr_t)dev->resource_list[0].base;
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graphics_base = dev->resource_list[2].base;
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printk(BIOS_SPEW, "GMADR = 0x%08x GTTADR = 0x%08x\n",
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pci_read_config32(dev, GMADR),
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pci_read_config32(dev, GTTADR)
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);
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int err;
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/* probe if VGA is connected and alway run */
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/* VGA init if no LVDS is connected */
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if (!probe_edid(mmiobase, 3) || probe_edid(mmiobase, 2))
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err = intel_gma_init_vga(conf,
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pci_read_config32(dev, 0x5c) & ~0xf,
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iobase, mmiobase, graphics_base);
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else
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err = intel_gma_init_lvds(conf,
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pci_read_config32(dev, 0x5c) & ~0xf,
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iobase, mmiobase, graphics_base);
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if (err == 0)
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gfx_set_init_done(1);
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/* Linux relies on VBT for panel info. */
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if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) {
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generate_fake_intel_oprom(&conf->gfx, dev,
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"$VBT CALISTOGA");
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}
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if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) {
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generate_fake_intel_oprom(&conf->gfx, dev,
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"$VBT LAKEPORT-G");
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}
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}
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#endif
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}
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/* This doesn't reclaim stolen UMA memory, but IGD could still
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