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nb/intel/sandybridge: Remove variable set but not used 

Change-Id: I75f5d821e018932d3f10d84b7ebed362777fb17d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32938
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2019-05-22 19:57:43 +02:00 committed by Patrick Georgi
parent fa1f7216ce
commit 9c8895fd88
1 changed files with 6 additions and 12 deletions
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18
src/northbridge/intel/sandybridge/raminit_common.c
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@ -1452,9 +1452,8 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
int lane; int lane;
FOR_ALL_LANES { FOR_ALL_LANES {
volatile u32 tmp;
MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0;
tmp = MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); MCHBAR32(0x4140 + 0x400 * channel + 4 * lane);
} }
wait_428c(channel); wait_428c(channel);
@ -2026,9 +2025,8 @@ int write_training(ramctr_timing * ctrl)
MCHBAR32_OR(0x5030, 8); MCHBAR32_OR(0x5030, 8);
FOR_ALL_POPULATED_CHANNELS { FOR_ALL_POPULATED_CHANNELS {
volatile u32 tmp;
MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000); MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000);
tmp = MCHBAR32(0x428c + 0x400 * channel); MCHBAR32(0x428c + 0x400 * channel);
wait_428c(channel); wait_428c(channel);
/* DRAM command ZQCS */ /* DRAM command ZQCS */
@ -2373,9 +2371,8 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank,
program_timings(ctrl, channel); program_timings(ctrl, channel);
FOR_ALL_LANES { FOR_ALL_LANES {
volatile u32 tmp;
MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0;
tmp = MCHBAR32(0x400 * channel + 4 * lane + 0x4140); MCHBAR32(0x400 * channel + 4 * lane + 0x4140);
} }
wait_428c(channel); wait_428c(channel);
@ -2454,8 +2451,7 @@ int discover_edges(ramctr_timing *ctrl)
fill_pattern0(ctrl, channel, 0, 0); fill_pattern0(ctrl, channel, 0, 0);
MCHBAR32(0x4288 + (channel << 10)) = 0; MCHBAR32(0x4288 + (channel << 10)) = 0;
FOR_ALL_LANES { FOR_ALL_LANES {
volatile u32 tmp; MCHBAR32(0x400 * channel + lane * 4 + 0x4140);
tmp = MCHBAR32(0x400 * channel + lane * 4 + 0x4140);
} }
FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
@ -2655,10 +2651,9 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel,
program_timings(ctrl, channel); program_timings(ctrl, channel);
FOR_ALL_LANES { FOR_ALL_LANES {
volatile u32 tmp;
MCHBAR32(0x4340 + 0x400 * channel + MCHBAR32(0x4340 + 0x400 * channel +
4 * lane) = 0; 4 * lane) = 0;
tmp = MCHBAR32(0x400 * channel + MCHBAR32(0x400 * channel +
4 * lane + 0x4140); 4 * lane + 0x4140);
} }
wait_428c(channel); wait_428c(channel);
@ -2703,8 +2698,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel,
wait_428c(channel); wait_428c(channel);
FOR_ALL_LANES { FOR_ALL_LANES {
volatile u32 tmp; MCHBAR32(0x4340 +
tmp = MCHBAR32(0x4340 +
0x400 * channel + lane * 4); 0x400 * channel + lane * 4);
} }