hdama mainboard and target.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
c55613345e
commit
9c8a06a379
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@ -15,6 +15,9 @@ The goals of the new language are these:
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a bit more comprehensible and flexible
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a bit more comprehensible and flexible
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\item make the specification easier for people to use and understand
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\item make the specification easier for people to use and understand
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\item allow unique register-set-specifiers for each chip
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\item allow unique register-set-specifiers for each chip
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\item allow generic register-set-specifiers for each chip
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\item generate static initialization code, as needed, for the
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specifiers.
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\end{itemize}
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\end{itemize}
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\section{Language}
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\section{Language}
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@ -143,6 +146,27 @@ board ::= target (option)* mainboard
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\end{verbatim}
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\end{verbatim}
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\subsubsection{Command definitions}
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\subsubsubsection{option}
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\subsubsubsection{default}
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\subsubsubsection{cpu}
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\subsubsubsection{arch}
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\subsubsubsection{northbridge}
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\subsubsubsection{southbridge}
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\subsubsubsection{superio}
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\subsubsubsection{object}
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\subsubsubsection{driver}
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\subsubsubsection{mainboardinit}
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\subsubsubsection{makerule}
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\subsubsubsection{makedefine}
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\subsubsubsection{addaction}
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\subsubsubsection{init}
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\subsubsubsection{register}
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\subsubsubsection{iif}
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\subsubsubsection{dir}
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\subsubsubsection{ldscript}
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A sample file:
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A sample file:
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\begin{verbatim}
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\begin{verbatim}
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@ -0,0 +1,133 @@
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#
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#
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###
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### Set all of the defaults for an x86 architecture
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###
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#
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#
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###
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### Build the objects we have code for in this directory.
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###
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##object mainboard.o
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driver mainboard.o
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object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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arch i386 end
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cpu k8 end
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#
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option DEBUG=1
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default USE_FALLBACK_IMAGE=1
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option A=(1+2)
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option B=0xa
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#
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###
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### Build our 16 bit and 32 bit linuxBIOS entry code
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###
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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#
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###
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### Build our reset vector (This is where linuxBIOS is entered)
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###
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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end
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if USE_NORMAL_IMAGE
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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#
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#### Should this be in the northbridge code?
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#mainboardinit archi386/lib/cpu_reset.inc
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#
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###
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### Include an id string (For safe flashing)
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###
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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#
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####
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#### This is the early phase of linuxBIOS startup
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#### Things are delicate and we test to see if we should
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#### failover to another image.
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####
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option MAX_REBOOT_CNT=2
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##ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE
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#
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###
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### Setup our mtrrs
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###
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mainboardinit cpu/k8/earlymtrr.inc
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#
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#
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###
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### Only the bootstrap cpu makes it here.
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### Failover if we need to
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###
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#
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if USE_FALLBACK_IMAGE
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mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
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end
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#
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####
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#### O.k. We aren't just an intermediary anymore!
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####
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#
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###
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### When debugging disable the watchdog timer
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###
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##option MAXIMUM_CONSOLE_LOGLEVEL=7
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#default MAXIMUM_CONSOLE_LOGLEVEL=7
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#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
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#if DISABLE_WATCHDOG
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# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
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#end
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#
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###
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### Setup the serial port
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###
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#mainboardinit superiowinbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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if USE_FALLBACK_IMAGE mainboardinit archi386/lib/noop_failover.inc end
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#
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###
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### Romcc output
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###
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#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
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#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
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#mainboardinit .failover.inc
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makerule ./auto.E dep "$(MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
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mainboardinit ./auto.inc
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#
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###
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### Setup RAM
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###
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mainboardinit ram/ramtest.inc
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mainboardinit southbridge/amd/amd8111/smbus.inc
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mainboardinit sdram/generic_dump_spd.inc
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#
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###
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### Include the secondary Configuration files
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###
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northbridge amd/amdk8
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end
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southbridge amd/amd8111
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end
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#mainboardinit archi386/smp/secondary.inc
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superio NSC/pc87360
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register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
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end
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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cpu p5 end
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cpu p6 end
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cpu k7 end
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cpu k8 end
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,74 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 1007 1008
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@ -0,0 +1,31 @@
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/* This file was generated by getpir.c, do not modify!
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(but if you do, please run checkpir on it to verify)
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Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
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Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*7, /* there can be total 7 devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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(5<<3)|3, /* Where the interrupt router lies (dev) */
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0xc20, /* IRQs devoted exclusively to PCI usage */
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0x1022, /* Vendor */
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0x746b, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0xdf, /* u8 checksum , mod 256 checksum must give zero */
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{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x02, (5<<3)|0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}}, 0x02, 0x00},
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{0x02, (6<<3)|0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}}, 0x03, 0x00},
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{0x02, (7<<3)|0, {{0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}}, 0x04, 0x00},
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{0x02, (1<<3)|1, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}}, 0x00, 0x00},
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{0x00, (5<<3)|1, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x00, 0x00},
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{0x00, (2<<3)|0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x00, 0x00},
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{0xff, 0xff, {{0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}}, 0xff, 0xff},
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}
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};
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@ -0,0 +1,137 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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unsigned long initial_apicid[MAX_CPUS] =
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{
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0
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};
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void
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mainboard_fixup(void)
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{
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}
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void
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final_mainboard_fixup(void)
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{
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#if 0
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// void final_southbridge_fixup(void);
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// void final_superio_fixup(void);
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printk_info("AMD Solo initializing...");
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// final_southbridge_fixup();
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//#ifndef USE_NEW_SUPERIO_INTERFACE
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//final_superio_fixup();
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//#endif
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#endif
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}
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struct ioapicreg {
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unsigned int reg;
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unsigned int value_low, value_high;
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};
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static struct ioapicreg ioapicregvalues[] = {
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#define ALL (0xff << 24)
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#define NONE (0)
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#define DISABLED (1 << 16)
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#define ENABLED (0 << 16)
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#define TRIGGER_EDGE (0 << 15)
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#define TRIGGER_LEVEL (1 << 15)
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#define POLARITY_HIGH (0 << 13)
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#define POLARITY_LOW (1 << 13)
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#define PHYSICAL_DEST (0 << 11)
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#define LOGICAL_DEST (1 << 11)
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#define ExtINT (7 << 8)
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#define NMI (4 << 8)
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#define SMI (2 << 8)
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#define INT (1 << 8)
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/* mask, trigger, polarity, destination, delivery, vector */
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{0x00, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT | 0, 0},
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{0x01, DISABLED, NONE},
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{0x02, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | INT | 0, 0},
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{0x03, DISABLED, NONE},
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{0x04, DISABLED, NONE},
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{0x05, DISABLED, NONE},
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{0x06, DISABLED, NONE},
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{0x07, DISABLED, NONE},
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{0x08, DISABLED, NONE},
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{0x09, DISABLED, NONE},
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{0x0a, DISABLED, NONE},
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{0x0b, DISABLED, NONE},
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{0x0c, DISABLED, NONE},
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{0x0d, DISABLED, NONE},
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{0x0e, DISABLED, NONE},
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{0x0f, DISABLED, NONE},
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{0x10, DISABLED, NONE},
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{0x11, DISABLED, NONE},
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{0x12, DISABLED, NONE},
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{0x13, DISABLED, NONE},
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{0x14, DISABLED, NONE},
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{0x14, DISABLED, NONE},
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{0x15, DISABLED, NONE},
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{0x16, DISABLED, NONE},
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{0x17, DISABLED, NONE},
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{0x18, DISABLED, NONE},
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{0x19, DISABLED, NONE},
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{0x20, DISABLED, NONE},
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{0x21, DISABLED, NONE},
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{0x22, DISABLED, NONE},
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{0x23, DISABLED, NONE},
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};
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||||||
|
static void setup_ioapic(void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
unsigned long value_low, value_high;
|
||||||
|
unsigned long ioapic_base = 0xfec00000;
|
||||||
|
volatile unsigned long *l;
|
||||||
|
struct ioapicreg *a = ioapicregvalues;
|
||||||
|
|
||||||
|
l = (unsigned long *) ioapic_base;
|
||||||
|
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
|
||||||
|
i++, a++) {
|
||||||
|
l[0] = (a->reg * 2) + 0x10;
|
||||||
|
l[4] = a->value_low;
|
||||||
|
value_low = l[4];
|
||||||
|
l[0] = (a->reg *2) + 0x11;
|
||||||
|
l[4] = a->value_high;
|
||||||
|
value_high = l[4];
|
||||||
|
if ((i==0) && (value_low == 0xffffffff)) {
|
||||||
|
printk_warning("IO APIC not responding.\n");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
|
||||||
|
a->reg, a->value_low, a->value_high);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void lpc_init(struct device *dev)
|
||||||
|
{
|
||||||
|
uint8_t byte;
|
||||||
|
printk_debug("lpc_init\n");
|
||||||
|
#if 0
|
||||||
|
pci_read_config_byte(dev, 0x4B, &byte);
|
||||||
|
byte |= 1;
|
||||||
|
pci_write_config_byte(dev, 0x4B, byte);
|
||||||
|
setup_ioapic();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct device_operations lpc_ops = {
|
||||||
|
.read_resources = pci_dev_read_resources,
|
||||||
|
.set_resources = pci_dev_set_resources,
|
||||||
|
.init = lpc_init,
|
||||||
|
.scan_bus = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct pci_driver lpc_driver __pci_driver = {
|
||||||
|
.ops = &lpc_ops,
|
||||||
|
.vendor = PCI_VENDOR_ID_AMD,
|
||||||
|
.device = 0x7468,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,118 @@
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <arch/smp/mpspec.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||||
|
{
|
||||||
|
static const char sig[4] = "PCMP";
|
||||||
|
static const char oem[8] = "LNXI ";
|
||||||
|
static const char productid[12] = "P4DPR ";
|
||||||
|
struct mp_config_table *mc;
|
||||||
|
|
||||||
|
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||||
|
memset(mc, 0, sizeof(*mc));
|
||||||
|
|
||||||
|
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||||
|
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||||
|
mc->mpc_spec = 0x04;
|
||||||
|
mc->mpc_checksum = 0; /* not yet computed */
|
||||||
|
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||||
|
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||||
|
mc->mpc_oemptr = 0;
|
||||||
|
mc->mpc_oemsize = 0;
|
||||||
|
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||||
|
mc->mpc_lapic = LAPIC_ADDR;
|
||||||
|
mc->mpe_length = 0;
|
||||||
|
mc->mpe_checksum = 0;
|
||||||
|
mc->reserved = 0;
|
||||||
|
|
||||||
|
smp_write_processors(mc, processor_map);
|
||||||
|
|
||||||
|
smp_write_bus(mc, 0, "PCI ");
|
||||||
|
smp_write_bus(mc, 1, "PCI ");
|
||||||
|
smp_write_bus(mc, 2, "PCI ");
|
||||||
|
smp_write_bus(mc, 3, "ISA ");
|
||||||
|
|
||||||
|
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||||
|
|
||||||
|
/* ISA backward compatibility interrupts */
|
||||||
|
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x00, 0x02, 0x00);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x01, 0x02, 0x01);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x00, 0x02, 0x02);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x03, 0x02, 0x03);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x04, 0x02, 0x04);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||||
|
0x03, 0x05, 0x02, 0x05);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x06, 0x02, 0x06);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x07, 0x02, 0x07);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||||
|
0x03, 0x08, 0x02, 0x08);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x09, 0x02, 0x09);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||||
|
0x03, 0x0a, 0x02, 0x0a);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||||
|
0x03, 0x0b, 0x02, 0x0b);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x0c, 0x02, 0x0c);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x0d, 0x02, 0x0d);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x0e, 0x02, 0x0e);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x0f, 0x02, 0x0f);
|
||||||
|
|
||||||
|
/* Standard local interrupt assignments */
|
||||||
|
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x03, 0x00, MP_APIC_ALL, 0x00);
|
||||||
|
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x00, 0x00, MP_APIC_ALL, 0x01);
|
||||||
|
|
||||||
|
|
||||||
|
/* 8111 DevB.3 */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x00, (5<<2)|3, 0x02, 0x13);
|
||||||
|
|
||||||
|
/* AGP Slot */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x01, (0<<2)|0, 0x02, 0x10);
|
||||||
|
|
||||||
|
/* PCI Slot 1 */
|
||||||
|
/* PCI Slot 2 */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x02, (5 <<2)|0, 0x02, 0x11);
|
||||||
|
/* PCI Slot 3 */
|
||||||
|
/* PCI Slot 4 */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x02, (7<<2)|0, 0x02, 0x13);
|
||||||
|
|
||||||
|
/* AMR Slot */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
0x02, (1<<2)|0, 0x02, 0x10);
|
||||||
|
|
||||||
|
/* There is no extension information... */
|
||||||
|
|
||||||
|
/* Compute the checksums */
|
||||||
|
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||||
|
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||||
|
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||||
|
mc, smp_next_mpe_entry(mc));
|
||||||
|
return smp_next_mpe_entry(mc);
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||||
|
{
|
||||||
|
void *v;
|
||||||
|
v = smp_write_floating_table(addr);
|
||||||
|
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,173 @@
|
||||||
|
# Sample config file for Motorola Sandpoint X3 Demo Board with
|
||||||
|
# the Arima HDAMA
|
||||||
|
# This will make a target directory of ./hdama
|
||||||
|
|
||||||
|
loadoptions
|
||||||
|
|
||||||
|
target ./hdama
|
||||||
|
|
||||||
|
uses CONFIG_COMPRESS
|
||||||
|
uses CONFIG_IOAPIC
|
||||||
|
uses CONFIG_ROM_STREAM
|
||||||
|
uses CONFIG_ROM_STREAM_START
|
||||||
|
uses ENABLE_FIXED_AND_VARIABLE_MTRRS
|
||||||
|
uses FINAL_MAINBOARD_FIXUP
|
||||||
|
uses HAVE_FALLBACK_BOOT
|
||||||
|
uses HAVE_PIRQ_TABLE
|
||||||
|
uses HEAP_SIZE
|
||||||
|
uses IRQ_SLOT_COUNT
|
||||||
|
uses MAINBOARD_PART_NUMBER
|
||||||
|
uses MAINBOARD_VENDOR
|
||||||
|
uses MAX_CPUS
|
||||||
|
uses MEMORY_HOLE
|
||||||
|
uses PAYLOAD_SIZE
|
||||||
|
uses _RAMBASE
|
||||||
|
uses _ROMBASE
|
||||||
|
uses ROM_IMAGE_SIZE
|
||||||
|
uses ROM_SECTION_OFFSET
|
||||||
|
uses ROM_SECTION_SIZE
|
||||||
|
uses ROM_SIZE
|
||||||
|
uses SIO_BASE
|
||||||
|
uses SIO_SYSTEM_CLK_INPUT
|
||||||
|
uses STACK_SIZE
|
||||||
|
uses USE_ELF_BOOT
|
||||||
|
uses USE_FALLBACK_IMAGE
|
||||||
|
uses USE_OPTION_TABLE
|
||||||
|
|
||||||
|
### Customize our winbond superio chip for this motherboard
|
||||||
|
###
|
||||||
|
option SIO_BASE=0x2e
|
||||||
|
option SIO_SYSTEM_CLK_INPUT=0
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### Build code for the fallback boot
|
||||||
|
###
|
||||||
|
option HAVE_FALLBACK_BOOT=1
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### Build code to export a programmable irq routing table
|
||||||
|
###
|
||||||
|
option HAVE_PIRQ_TABLE=1
|
||||||
|
option IRQ_SLOT_COUNT=7
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### Build code for SMP support
|
||||||
|
### Only worry about 2 micro processors
|
||||||
|
###
|
||||||
|
##option CONFIG_SMP=1
|
||||||
|
option MAX_CPUS=1
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### Build code to setup a generic IOAPIC
|
||||||
|
###
|
||||||
|
option CONFIG_IOAPIC=1
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### MEMORY_HOLE instructs earlymtrr.inc to
|
||||||
|
### enable caching from 0-640KB and to disable
|
||||||
|
### caching from 640KB-1MB using fixed MTRRs
|
||||||
|
###
|
||||||
|
### Enabling this option breaks SMP because secondary
|
||||||
|
### CPU identification depends on only variable MTRRs
|
||||||
|
### being enabled.
|
||||||
|
###
|
||||||
|
option MEMORY_HOLE=0
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### Enable both fixed and variable MTRRS
|
||||||
|
### When we setup MTRRs in mtrr.c
|
||||||
|
###
|
||||||
|
### We must setup the fixed mtrrs or we confuse SMP secondary
|
||||||
|
### processor identification
|
||||||
|
###
|
||||||
|
option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### Clean up the motherboard id strings
|
||||||
|
###
|
||||||
|
option MAINBOARD_PART_NUMBER="Solo7"
|
||||||
|
option MAINBOARD_VENDOR="AMD"
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### Call the final_mainboard_fixup function
|
||||||
|
###
|
||||||
|
option FINAL_MAINBOARD_FIXUP=1
|
||||||
|
option USE_FALLBACK_IMAGE=0
|
||||||
|
|
||||||
|
###
|
||||||
|
### Only use the option table in a normal image
|
||||||
|
###
|
||||||
|
option USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### Compute the location and size of where this firmware image
|
||||||
|
### (linuxBIOS plus bootloader) will live in the boot rom chip.
|
||||||
|
###
|
||||||
|
if USE_FALLBACK_IMAGE
|
||||||
|
option ROM_SECTION_SIZE = FALLBACK_SIZE
|
||||||
|
option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
|
||||||
|
end
|
||||||
|
if USE_NORMAL_IMAGE
|
||||||
|
option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
|
||||||
|
option ROM_SECTION_OFFSET= 0
|
||||||
|
end
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### Compute the start location and size size of
|
||||||
|
### The linuxBIOS bootloader.
|
||||||
|
###
|
||||||
|
option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
|
||||||
|
option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
|
||||||
|
option CONFIG_ROM_STREAM = 1
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### Compute where this copy of linuxBIOS will start in the boot rom
|
||||||
|
###
|
||||||
|
option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
|
||||||
|
#
|
||||||
|
###
|
||||||
|
### Compute a range of ROM that can cached to speed up linuxBIOS,
|
||||||
|
### execution speed.
|
||||||
|
###
|
||||||
|
##expr XIP_ROM_SIZE = 65536
|
||||||
|
##expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
|
||||||
|
##option XIP_ROM_SIZE=65536
|
||||||
|
##option XIP_ROM_BASE=0xffff0000
|
||||||
|
#
|
||||||
|
## XIP_ROM_SIZE && XIP_ROM_BASE values that work.
|
||||||
|
##option XIP_ROM_SIZE=0x8000
|
||||||
|
##option XIP_ROM_BASE=0xffff8000
|
||||||
|
|
||||||
|
## We don't use compressed image
|
||||||
|
option CONFIG_COMPRESS=0
|
||||||
|
|
||||||
|
option USE_ELF_BOOT=1
|
||||||
|
|
||||||
|
option ROM_SIZE=524288
|
||||||
|
|
||||||
|
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||||
|
option ROM_IMAGE_SIZE=49152
|
||||||
|
|
||||||
|
## LinuxBIOS C code runs at this location in RAM
|
||||||
|
option _RAMBASE=0x00100000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Use a 64K stack
|
||||||
|
##
|
||||||
|
option STACK_SIZE=0x10000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Use a 64K heap
|
||||||
|
##
|
||||||
|
option HEAP_SIZE=0x10000
|
||||||
|
|
||||||
|
## Compute the location and size of where this firmware image
|
||||||
|
## (linuxBIOS plus bootloader) will live in the boot rom chip.
|
||||||
|
##
|
||||||
|
option ROM_SECTION_SIZE=ROM_SIZE
|
||||||
|
option ROM_SECTION_OFFSET=0
|
||||||
|
|
||||||
|
# Arima hdama
|
||||||
|
mainboard arima/hdama
|
||||||
|
makedefine CFLAGS += -g
|
||||||
|
end
|
||||||
Loading…
Reference in New Issue