coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at init
Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR registers should be done with proper bitmask. BUG=None BRANCH=None TEST=Compiles successfully and verified that the RES bits are preserved across register writes. Original-Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207815 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit dfb196b4063e4f94d1ba9d5e2d19bae624ed46b3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I033a68b723fea83817aaa6402b86c78abd3e1da9 Reviewed-on: http://review.coreboot.org/8592 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
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@ -21,9 +21,17 @@
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#include <arch/asm.h>
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#include <arch/asm.h>
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ENTRY(arm64_el3_startup)
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ENTRY(arm64_el3_startup)
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mov x0, xzr
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/* Set all bits in SCTLR_EL3 to 0 except RES1 and RES0 */
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mrs x0, SCTLR_EL3
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ldr x1, .SCTLR_MASK
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and x0, x0, x1
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msr SCTLR_EL3, x0
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msr SCTLR_EL3, x0
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msr SCR_EL3, x0
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/* Set all bits in SCR_EL3 to 0 except RES1 and RES0 */
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mrs x0, SCR_EL3
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ldr x1, .SCR_MASK
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and x0, x0, x1
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msr SCR_EL3, x0
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/* Have stack pointer use SP_EL0. */
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/* Have stack pointer use SP_EL0. */
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msr SPSel, #0
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msr SPSel, #0
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isb
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isb
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@ -38,6 +46,12 @@ ENTRY(arm64_el3_startup)
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ldr x1, .entry
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ldr x1, .entry
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br x1
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br x1
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.align 4
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.SCTLR_MASK:
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.quad 0x0FFFFEFF0
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.SCR_MASK:
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.quad 0x0FFFFC070
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.align 4
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.align 4
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/*
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/*
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* By default branch to main() and initialize the stack according
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* By default branch to main() and initialize the stack according
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