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inteltool: Add Intel 4-Series chipset detection 

Previously, X4X was incorrectly named because it provides
support for SKUs within XX4X range.  This is renamed.

This patch provides support for all X4X SKUs according to
datasheet Intel 4 Series Chipset Family Specification Update,
namely: Q45, Q43, P45, P43, G45, G43, G41 and B43 (both versions).

Tested on Gigabyte GA-G41M-ES2L

Change-Id: I032265e80d9ca51e2fef29201280832ea3210a0b
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/11245
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Damien Zammit 2015-08-17 21:04:41 +10:00 committed by Alexandru Gagniuc
parent fdbc1af5e2
commit 9c98664480
4 changed files with 37 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
util/inteltool/inteltool.c
View File

@ -61,7 +61,12 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X4X, "GL40/GS40/GM45/GS45/PM45" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82XX4X, "GL40/GS40/GM45/GS45/PM45" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q45, "Q45/Q43" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G45, "G45/G43/P45/P43" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G41, "G41" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82B43, "B43 (Base)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82B43_2, "B43 (Soft)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" },

8
util/inteltool/inteltool.h
View File

@ -132,7 +132,13 @@
#define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0
#define PCI_DEVICE_ID_INTEL_82X38 0x29e0 #define PCI_DEVICE_ID_INTEL_82X38 0x29e0
#define PCI_DEVICE_ID_INTEL_32X0 0x29f0 #define PCI_DEVICE_ID_INTEL_32X0 0x29f0
#define PCI_DEVICE_ID_INTEL_82X4X 0x2a40 #define PCI_DEVICE_ID_INTEL_82XX4X 0x2a40
#define PCI_DEVICE_ID_INTEL_82Q45 0x2e10
#define PCI_DEVICE_ID_INTEL_82G45 0x2e20
#define PCI_DEVICE_ID_INTEL_82G41 0x2e30
#define PCI_DEVICE_ID_INTEL_82B43 0x2e40
#define PCI_DEVICE_ID_INTEL_82B43_2 0x2e90
#define PCI_DEVICE_ID_INTEL_82X58 0x3405 #define PCI_DEVICE_ID_INTEL_82X58 0x3405
#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 #define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000

7
util/inteltool/memory.c
View File

@ -194,7 +194,12 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
case PCI_DEVICE_ID_INTEL_82830M: case PCI_DEVICE_ID_INTEL_82830M:
printf("This northbridge does not have MCHBAR.\n"); printf("This northbridge does not have MCHBAR.\n");
return 1; return 1;
case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_82XX4X:
case PCI_DEVICE_ID_INTEL_82Q45:
case PCI_DEVICE_ID_INTEL_82G45:
case PCI_DEVICE_ID_INTEL_82G41:
case PCI_DEVICE_ID_INTEL_82B43:
case PCI_DEVICE_ID_INTEL_82B43_2:
case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_82X38:
case PCI_DEVICE_ID_INTEL_32X0: case PCI_DEVICE_ID_INTEL_32X0:
mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;

21
util/inteltool/pcie.c
View File

@ -202,7 +202,12 @@ int print_epbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_82X38:
case PCI_DEVICE_ID_INTEL_32X0: case PCI_DEVICE_ID_INTEL_32X0:
case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_82XX4X:
case PCI_DEVICE_ID_INTEL_82Q45:
case PCI_DEVICE_ID_INTEL_82G45:
case PCI_DEVICE_ID_INTEL_82G41:
case PCI_DEVICE_ID_INTEL_82B43:
case PCI_DEVICE_ID_INTEL_82B43_2:
case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
case PCI_DEVICE_ID_INTEL_ATOM_NXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
@ -277,7 +282,12 @@ int print_dmibar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_82X38:
case PCI_DEVICE_ID_INTEL_32X0: case PCI_DEVICE_ID_INTEL_32X0:
case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_82XX4X:
case PCI_DEVICE_ID_INTEL_82Q45:
case PCI_DEVICE_ID_INTEL_82G45:
case PCI_DEVICE_ID_INTEL_82G41:
case PCI_DEVICE_ID_INTEL_82B43:
case PCI_DEVICE_ID_INTEL_82B43_2:
case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
case PCI_DEVICE_ID_INTEL_ATOM_NXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
@ -406,7 +416,12 @@ int print_pciexbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_82X38:
case PCI_DEVICE_ID_INTEL_32X0: case PCI_DEVICE_ID_INTEL_32X0:
case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_82XX4X:
case PCI_DEVICE_ID_INTEL_82Q45:
case PCI_DEVICE_ID_INTEL_82G45:
case PCI_DEVICE_ID_INTEL_82G41:
case PCI_DEVICE_ID_INTEL_82B43:
case PCI_DEVICE_ID_INTEL_82B43_2:
case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
case PCI_DEVICE_ID_INTEL_ATOM_NXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: