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siemens/mc_apl2: Change SERIRQ mode 

Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected.
By removing this entry from devicetree, the default value (quiet mode)
is used. The problem is described in Intel document 334820-007 under
point APL47.

Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31138
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer 2019-01-29 08:54:52 +01:00 committed by Patrick Georgi
parent ddf84986d5
commit 9ca43191ab
1 changed files with 0 additions and 1 deletions
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1
src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
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@ -5,7 +5,6 @@ chip soc/intel/apollolake
end end
register "sci_irq" = "SCIS_IRQ10" register "sci_irq" = "SCIS_IRQ10"
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Disable all clkreq of PCIe root ports as SMARC interface do not # Disable all clkreq of PCIe root ports as SMARC interface do not
# have this pins. # have this pins.