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this port is horribly broken and should not have been checked in. This patch 

gets us through config, but it fails during build because the original patch
duplicated some files for VIA systems.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2009-06-09 15:22:47 +00:00 committed by Stefan Reinauer
parent a88db7bb87
commit 9ca6ed548e
2 changed files with 23 additions and 22 deletions
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42
src/mainboard/via/epia-m700/Options.lb
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@ -72,17 +72,17 @@ uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT uses CONFIG_USE_INIT
uses MAX_RAM_SLOTS #uses MAX_RAM_SLOTS
uses USB_ENABLE #uses USB_ENABLE
uses EHCI_ENABLE #uses EHCI_ENABLE
uses HPET_ENABLE #uses HPET_ENABLE
uses USB_PORTNUM #uses USB_PORTNUM
uses FULL_ROM_SIZE #uses FULL_ROM_SIZE
uses FULL_ROM_BASE #uses FULL_ROM_BASE
uses PAYLOAD_IS_SEABIOS #uses PAYLOAD_IS_SEABIOS
uses VIACONFIG_TOP_SM_SIZE_MB #uses VIACONFIG_TOP_SM_SIZE_MB
uses VIACONFIG_VGA_PCI_10 #uses VIACONFIG_VGA_PCI_10
uses VIACONFIG_VGA_PCI_14 #uses VIACONFIG_VGA_PCI_14
## New options ## New options
default USE_DCACHE_RAM = 1 default USE_DCACHE_RAM = 1
@ -91,18 +91,18 @@ default DCACHE_RAM_BASE = 0xffef0000
# default DCACHE_RAM_BASE = 0xfec00000 # HPET may use this. # default DCACHE_RAM_BASE = 0xfec00000 # HPET may use this.
default DCACHE_RAM_SIZE = 8 * 1024 default DCACHE_RAM_SIZE = 8 * 1024
default CONFIG_USE_INIT = 0 default CONFIG_USE_INIT = 0
default MAX_RAM_SLOTS = 2 #default MAX_RAM_SLOTS = 2
default USB_ENABLE = 1 #default USB_ENABLE = 1
default EHCI_ENABLE = 1 #default EHCI_ENABLE = 1
default HPET_ENABLE = 1 #default HPET_ENABLE = 1
default USB_PORTNUM = 2 #default USB_PORTNUM = 2
default FULL_ROM_SIZE = 512 * 1024 #default FULL_ROM_SIZE = 512 * 1024
default FULL_ROM_BASE = (0xffffffff - FULL_ROM_SIZE + 1) #default FULL_ROM_BASE = (0xffffffff - FULL_ROM_SIZE + 1)
default VIACONFIG_TOP_SM_SIZE_MB = 0 #default VIACONFIG_TOP_SM_SIZE_MB = 0
# default VIACONFIG_VGA_PCI_10 = 0xd0000008 # default VIACONFIG_VGA_PCI_10 = 0xd0000008
# default VIACONFIG_VGA_PCI_14 = 0xfd000000 # default VIACONFIG_VGA_PCI_14 = 0xfd000000
default VIACONFIG_VGA_PCI_10 = 0xf8000008 #default VIACONFIG_VGA_PCI_10 = 0xf8000008
default VIACONFIG_VGA_PCI_14 = 0xfc000000 #default VIACONFIG_VGA_PCI_14 = 0xfc000000
default ROM_SIZE = 512 * 1024 default ROM_SIZE = 512 * 1024
default CONFIG_IOAPIC = 1 default CONFIG_IOAPIC = 1

3
src/northbridge/via/vx800/dram_init.h
View File

@ -110,7 +110,8 @@
#define SPD_DATA_SIZE 44 #define SPD_DATA_SIZE 44
//Dram cofig are //Dram cofig are
/*the most number of socket*/ /*the most number of socket*/
//#define MAX_RAM_SLOTS 2 #define MAX_RAM_SLOTS 2
#define MAX_SOCKETS MAX_RAM_SLOTS #define MAX_SOCKETS MAX_RAM_SLOTS
#define MAX_DIMMS MAX_SOCKETS /*every sockets can plug one DIMM */ #define MAX_DIMMS MAX_SOCKETS /*every sockets can plug one DIMM */
/*the most number of RANKs on a DIMM*/ /*the most number of RANKs on a DIMM*/