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soc/nvidia/tegra124: remove cache_policiy option 

All mainboards (nyans) utilizing the cache_policy option
has it set to DCACHE_WRITETHROUGH. This option is for setting
the framebuffer's cache attribute. However, this option is
reliant on an architecture-specific enumeration. Just remove
the option and use DCACHE_WRITETHROUGH across the board. If
someone wants to reconfigure it at a later date one can
introduce a non-architecture specific option.

Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Aaron Durbin 2016-07-25 11:30:43 -05:00
parent aa3e8a8124
commit 9cbc90a1f6
5 changed files with 1 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/nyan/devicetree.cb
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@ -32,8 +32,6 @@ chip soc/nvidia/tegra124
register "panel_bits_per_pixel" = "18"
register "cache_policy" = "DCACHE_WRITETHROUGH"
# With some help from the mainbaord designer
register "backlight_en_gpio" = "GPIO(H2)"
register "lvds_shutdown_gpio" = "0"

2
src/mainboard/google/nyan_big/devicetree.cb
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@ -32,8 +32,6 @@ chip soc/nvidia/tegra124
register "panel_bits_per_pixel" = "18"
register "cache_policy" = "DCACHE_WRITETHROUGH"
# With some help from the mainbaord designer
register "backlight_en_gpio" = "GPIO(H2)"
register "lvds_shutdown_gpio" = "0"

2
src/mainboard/google/nyan_blaze/devicetree.cb
View File

@ -32,8 +32,6 @@ chip soc/nvidia/tegra124
register "panel_bits_per_pixel" = "18"
register "cache_policy" = "DCACHE_WRITETHROUGH"
# With some help from the mainbaord designer
register "backlight_en_gpio" = "GPIO(H2)"
register "lvds_shutdown_gpio" = "0"

1
src/soc/nvidia/tegra124/chip.h
View File

@ -32,7 +32,6 @@ struct soc_nvidia_tegra124_config {
u32 framebuffer_bits_per_pixel;
u32 color_depth;
u32 panel_bits_per_pixel;
int cache_policy;
/* there are two. It's not unimaginable that we might someday
* have two of these structs in a single mainboard.
*/

2
src/soc/nvidia/tegra124/display.c
View File

@ -263,7 +263,7 @@ void display_startup(device_t dev)
config->framebuffer_base = framebuffer_base_mb * MiB;
mmu_config_range(framebuffer_base_mb, framebuffer_size_mb,
config->cache_policy);
DCACHE_WRITETHROUGH);
printk(BIOS_SPEW, "LCD frame buffer at %dMiB to %dMiB\n", framebuffer_base_mb,
framebuffer_base_mb + framebuffer_size_mb);