soc/amd/common/data_fabric/domain: use get_iohc_fabric_id

Use get_iohc_fabric_id() to translate the coreboot domain's number into
the destination data fabric ID of the PCI root. This allows using the
coreboot domain 0 as primary domain of the SoC in all cases, so it's
still possible to use config_of_soc(). This allows dropping the
SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN_MULTI_PCI_ROOT Kconfig option
and do the check if the destination fabric ID in the PCI bus number,
MMIO, and IO decode registers is the correct one for the domain without
the need to use a non-zero number for the primary PCI root domain.

TEST=Mandolin still boots and the PCI bus, IO and MMIO resources still
get reported correctly.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I880ee0bf5c185cfe4af7de0d39581eb951ee603a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77169
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/common/block/data_fabric/Kconfig

@@ -14,22 +14,6 @@ config SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
 	  fabric registers so that it knows in which regions it can properly
 	  allocate the non-fixed MMIO devices.
 
-config SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN_MULTI_PCI_ROOT
-	bool
-	depends on SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
-	help
-	  On AMD SoCs with more than one PCI root, make sure to only report the
-	  PCI bus number, IO, and MMIO resources that get decoded to a specific
-	  PCI root in the corresponding coreboot domain. This will make sure
-	  that the allocation the resoucre allocator calculates will be decoded
-	  correctly to the PCI roots. In order for coreboot to know the correct
-	  mapping, the coreboot domain numbers must be set to the corresponding
-	  data fabric destination ID. On AMD systems with only one PCI root,
-	  this isn't needed and even though selecting this option works when
-	  the coreboot domain numbers are set up correctly, some link-time
-	  optimizations won't be possible, so it's preferable to only select
-	  this option on SoCs with multiple PCI roots.
-
 config SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT
 	bool
 	depends on SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN

src/soc/amd/common/block/data_fabric/domain.c

@@ -94,6 +94,7 @@ static void report_data_fabric_mmio(struct device *domain, unsigned int idx,
 /* Tell the resource allocator about the usable MMIO ranges configured in the data fabric */
 static void add_data_fabric_mmio_regions(struct device *domain, unsigned int *idx)
 {
+	const signed int iohc_dest_fabric_id = get_iohc_fabric_id(domain);
 	union df_mmio_control ctrl;
 	resource_t mmio_base;
 	resource_t mmio_limit;
@@ -114,8 +115,7 @@ static void add_data_fabric_mmio_regions(struct device *domain, unsigned int *id
 			continue;
 
 		/* Only look at MMIO regions that are decoded to the right PCI root */
-		if (CONFIG(SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN_MULTI_PCI_ROOT) &&
-		    ctrl.dst_fabric_id != domain->path.domain.domain)
+		if (ctrl.dst_fabric_id != iohc_dest_fabric_id)
 			continue;
 
 		data_fabric_get_mmio_base_size(i, &mmio_base, &mmio_limit);
@@ -156,6 +156,7 @@ static void report_data_fabric_io(struct device *domain, unsigned int idx,
 /* Tell the resource allocator about the usable I/O space */
 static void add_data_fabric_io_regions(struct device *domain, unsigned int *idx)
 {
+	const signed int iohc_dest_fabric_id = get_iohc_fabric_id(domain);
 	union df_io_base base_reg;
 	union df_io_limit limit_reg;
 	resource_t io_base;
@@ -171,8 +172,7 @@ static void add_data_fabric_io_regions(struct device *domain, unsigned int *idx)
 		limit_reg.raw = data_fabric_broadcast_read32(DF_IO_LIMIT(i));
 
 		/* Only look at IO regions that are decoded to the right PCI root */
-		if (CONFIG(SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN_MULTI_PCI_ROOT) &&
-		    limit_reg.dst_fabric_id != domain->path.domain.domain)
+		if (limit_reg.dst_fabric_id != iohc_dest_fabric_id)
 			continue;
 
 		io_base = base_reg.io_base << DF_IO_ADDR_SHIFT;

src/soc/amd/common/block/data_fabric/pci_segment_multi.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/data_fabric.h>
+#include <amdblocks/root_complex.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <types.h>
@@ -8,6 +9,7 @@
 enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *first_bus,
 					    uint8_t *last_bus)
 {
+	const signed int iohc_dest_fabric_id = get_iohc_fabric_id(domain);
 	union df_pci_cfg_base pci_bus_base;
 	union df_pci_cfg_limit pci_bus_limit;
 
@@ -15,8 +17,7 @@ enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *firs
 		pci_bus_base.raw = data_fabric_broadcast_read32(DF_PCI_CFG_BASE(i));
 		pci_bus_limit.raw = data_fabric_broadcast_read32(DF_PCI_CFG_LIMIT(i));
 
-		if (CONFIG(SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN_MULTI_PCI_ROOT) &&
-		    pci_bus_limit.dst_fabric_id != domain->path.domain.domain)
+		if (pci_bus_limit.dst_fabric_id != iohc_dest_fabric_id)
 			continue;
 
 		if (pci_bus_base.we && pci_bus_base.re) {

src/soc/amd/common/block/data_fabric/pci_segment_single.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/data_fabric.h>
+#include <amdblocks/root_complex.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <types.h>
@@ -8,13 +9,13 @@
 enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *first_bus,
 					    uint8_t *last_bus)
 {
+	const signed int iohc_dest_fabric_id = get_iohc_fabric_id(domain);
 	union df_pci_cfg_map pci_bus_map;
 
 	for (unsigned int i = 0; i < DF_PCI_CFG_MAP_COUNT; i++) {
 		pci_bus_map.raw = data_fabric_broadcast_read32(DF_PCI_CFG_MAP(i));
 
-		if (CONFIG(SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN_MULTI_PCI_ROOT) &&
-		    pci_bus_map.dst_fabric_id != domain->path.domain.domain)
+		if (pci_bus_map.dst_fabric_id != iohc_dest_fabric_id)
 			continue;
 
 		if (pci_bus_map.we && pci_bus_map.re) {